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Fwd: Invitation to Ballot, P1076.1

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If you would like to participate in IEEE Standards Sponsor Ballot
Title: Standard VHDL Analog and Mixed-Signal Extensions
you must enroll as a member of the ballot group by 18-Apr-2017, 11:59 p.m. Eastern Time.

The IEEE Computer Society Society/Standard VHDL Analog and Mixed-Signal Extensions invites you to participate in the Revision Sponsor Ballot for:
Title: Standard VHDL Analog and Mixed-Signal Extensions
Scope: This standard defines the IEEE 1076.1(TM) language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. Informally called VHDL-AMS, (VHSIC Hardware Description Language for Analog and Mixed-Signal, where VHSIC stands for Very High Speed Integrated Circuits), the language is built on the IEEE 1076(TM)(VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

Purpose: To support the design and verification of complex electronic systems containing a mixture of analog and digital devices, the IEEE 1076.1(TM) language provides, as an extension of the IEEE VHDL 1076 language, a comprehensive set of capabilities for the description and simulation of mixed-signal and mixed-technology systems.
The revision adds selected new features to the language definition of the 1076.1-2007 standard, and updates the 1076.1-2007 standard to reflect changes in the VHDL 1076-2008 specification.


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