High Speed JTAG

 

High Speed JTAG

IEEE P1149.10 - High Speed Test Access Port

and On-chip Distribution Architecture

Working Group

Scope
This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload and a distribution architecture for converting the test data to/from on-chip test structures.
The standard re-uses existing High Speed I/O (HSIO) known in the industry for the High-Speed Test Access Port. The HSIO connects to an on-chip distribution architecture through a common interface. The scope includes the distribution architecture test logic and packet decoder logic. The objective of the distribution architecture and packet decoder is that it can be readily re-used with different Integrated Circuits (ICs) that host different HSIO technology such that the standard addresses as large a part of the industry as possible.
The scope includes IEEE 1149.1 Boundary Scan Description Language (BSDL) and Procedural Description Language (PDL) documentation which can be used for configuring a mission mode HSIO to a test mode compatible with the High Speed Test Access Port (HSTAP). The same BSDL and PDL can then be used to deliver high-speed data to the on-chip test structures.

Need  

Test time has always been an important metric for SoCs. The original 1149.1 test access port is fine for simple board interconnect but as on-chip operations via the 1149.1 TAP have increased it becomes inefficient for board test and on-board FPGA configuration. The 1149.1 TAP has always been too slow for production SoC test. Wide TAMs ( Test Access Mechanisms) are used to increase test throughput during production at the cost of requiring more tester resources. Wide TAMs are also not useful for test re-use at board/system. A High-Speed Test Access Port and distribution matrix is needed by the industry to standardize a faster test data delivery mechanism which also can be re-used at the board level. This mechanism can transfer data for SoC test or FPGA configuration.

  
High Speed JTAG

Benefits

  • High-Bandwidth test data to/from IC or 3DSIC

 
  • Shorter test and configuration times
  • LPCT - Low Pin Count interface

 
  • Potential for lower scan clock rate
  • Potential for lower compressison factors

 
  • Simpler ATE pin electronics

discussionTechnical Proposals and Discussion

  restricted access
  Feb 22, 2015
  June 15th, 2015
  May 4th, 2015
  Feb 23th, 2015
  Feb 23th, 2015
  March 17th, 2014
  March 10th, 2014
  February 24, 2014
  January 27th, 2014
  January 13th, 2014
  November 25th, 2013
  November 11th, 2013
  October 14th, 2013
  October 7th, 2013
 

September 23rd, 2013

  August 19th, 2013
     

membersWG records

High-Speed JTAG - IEEE P1149.10 Meeting Minutes