* Real measurements of real components (more than simple resistors) * Will signal to noise be acceptable for 1 mA and 100 mV max, with leakages? * Do we need to measure G & +V switch impedance ever? * Could a bipolar IC really be dot4 compliant? Is CMOS-friendly good enough? * Do we really have no issues with draft 6 (= draft 5 + WG motions passed)? ------------------------------------------------------------------------------ Here you are just being pernickety! ------------------------------------------------------------------------------ Although no specific motions were passed by the WG, the main point to stress is that a digital pin can only have one of *two* intended voltages, to ensure its value can be captured by a single register bit. Multi-level (ternary, ...) logic pins would be declared as analog. ------------------------------------------------------------------------------ Perhaps there should be a section on implementation, to include not only the switch resistance issues but also ESD protection. ------------------------------------------------------------------------------ > * In Fig 4 page 11, probably the +V/G/VH/VL can be left out altogether, > since they are permitted to be pin-specific. OK. I will not change this at the moment (time....) but it can go into D07 if others agree. ------------------------------------------------------------------------------ I would like to discuss at the meeting each of the diagrams (and tables) in D06 with a view to finalising them. I would also like to go through the draft page by page so that we can at least identify where further editing will be necessary. ------------------------------------------------------------------------------ Designers will have a choice re differential logic pins, I guess. They can go with 1149.1 rules, or P1149.4 rules. The .4 rules should be consistent with the Feb'96 WG meeting's motions (note the second motion, w.r.t. optional .1 cell at single/differential interface): ------------------------------------------------------------------------------ Would all attendees please consider the following order (by reference to D05)? Clauses 1 - 3 Clauses 4, 4.1, 4.2 Clause 6.1 with additional paragraph added to the Description. This would mention the boundary-scan register and introduce the terms ABM and DBM. It would be similar in extent and intent to the existing paragraph at the end of 6.1 mentioning the bypass register. Clause 7 (including all sub-clauses) Clause 4.3 Clause 5 Clause 6.2 (including sub-clauses) I *think* this ordering would mean that the main terms would be defined before being referred to, but I fear that a certain amount of forward referencing is probably inevitable. I hope attendees at the meeting will look at this suggestion in detail and bring forward their comments. ------------------------------------------------------------------------------ > Do we really mean for the ETAP to "contain any number of additional analog > bus lines"? This looks like anarchy to software. ------------------------------------------------------------------------------ > A question for the working group: refering to figure 6 which shows the > switching for the AT-bus to the AB-bus, at one time we were going to > have a symetric interface, looking the same for both AT1 and AT2. Figure > 6 shows a non-symetric structure that appears to save a couple of switches. > It seems to me that switch pair (S1-S6) should always be complementary, > one on and one off, so that AB1 is always connected either to the outside > world, or to the DC voltage. However, to connect AB2 to the DC voltage, > I have to first connect AB1 to the DC voltage, close S3 and open S2. > Is there a scenario where I'm using only AT1 and want AB2 held quiet? > I can't do it with this setup. If we have independent switches for > connecting the DC voltage, we would be more general, and symetric too. > Ditto for +V, G, and the digitizer. It seems a trivial amount of circuitry > since there is only one occurance per IC. This circuit was discussed earlier over the air waves. It now appears that the switch S6 and the voltage "DC" may be in doubt. This is another point to be raised (and decided) at the next meeting. ------------------------------------------------------------------------------ > I was confused by the last paragraph in 6.2.1. (I also lost most of > figure 8 in translation.) What does it mean? This is the question of internal "boundary" cells (I mean modules). I am not quite sure what the final position is, either in dot1 or in dot4. I would welcome comment. ------------------------------------------------------------------------------ > Last sentence of 6.2.3.2 says "selection would be determined by a control > signal derived from the instruction controller". Well, how?? Does this > imply 2 flavors of EXTEST, ATEST, etc? I have never been happy with this. It is largely the brain-child of Steve. I assumed that the reason that I could not really get to grips with it was just a matter of being thick. However, if others also find this bit unclear, we should attempt to resolve it at the next meeting. ------------------------------------------------------------------------------ > AFUNCTION: Places Boundary Register in TDI/TDO path... Agree with all this > (Can anyone say S2 and S3 switches should be allowed/disallowed > as well??). My own feeling is that S2 and S3 should be open. ------------------------------------------------------------------------------ Looking again at your email and also Ken's, I have a query. You have the following. > S1=CD, S2=VH, S3=VL, S4=AB1, S5=AB2, M=Mode, F=Amode, * indicates inversion > S1 = M* > S2 = MXY > S3 = MX*Y > S4 = FXY* > S5 = FZ > Mandatory > Instructions AMode Mode > BYPASS 0 0 > SAMPLE 0 0 > EXTEST 1 1 > ATEST 1 0 You have AMODE = 1 in EXTEST, while Ken had it = 0. Is this change deliberate? I notice that in the switch equations Ken had (F + M) where you have F. With your value of AMODE, the simpler equation seems to be valid. Is there any reason not to use it? > 1149.1 Usage P1149.4 Usage > X=bit1, pin state, both drive & receive connect AB1 to pin > Y=bit2, tristate enable not used, must be 0 > Z=bit3, not used, must be 0 connect AB2 to pin These functions do not seem to tie up with either fig 10 or with the equations. (X does not control S4 (AB1)). ------------------------------------------------------------------------------ -------------------------- Clause 1.2 (page 6) last sentence before Figure 2: I'd change "decoupling capacitors" to "filter capacitors" to eliminate the implication that .4 can test power supply bypass capacitors. -------------------------- At the very end of 1.2, I'd add this: "The addition of designer-defined test functions is in no other way limited by this standard. This standard is intended to facilitate the incorporation of Ad Hoc testability features within the internal core structure as a designer sees fit." -------------------------- To reflect the importance of precise documentation of an 1149.4 implementation we will need to mandate how this is done. Without it, .4 is useless to anyone beyond the individuals designing ICs. In clause 1.3, we will need to add (d) Documentation of the implementation in BSDL (and other info?) as given in clause ?. -------------------------- We need to add a documentation clause per the previous observation. This will need to enumerate changes to BSDL needed to support .4, and very possibly also need to document analog properties of the IC, such as internal intra-pin and inter-pin impedances that cannot be disconnected. This is a major piece of work only fuzzily addressed by the WG to date. As we home in on the details of .4 silicon, we will be able to specify the documentation requirements. Without this clause, I do not feel that .4 can go to ballot. For background on this, see 1149.1, clause 12. -------------------------- Definition 3.5: I'm not sure how the IEEE defines differential signaling (which is what is carried on differential interconnect) but (to me) it implies mirror-symetrical signals, rather than just a pair of signals. -------------------------- Definition 3.6: Add "A digital boundary module may contain one or more boundary register cells as explained in 1149.1 Clause 10." to the end of the definition. Note also that a DBM may be interposed at the boundary between digital and analog portions of a mixed-signal IC. -------------------------- Note (1) on page 8 following Def 3.7: change "operate" to "represent data". -------------------------- Def 3.8 seems to imply that ANY object on a board (like a conventional IC not containing BScan) is a discrete device. "Discrete" devices seem to be packaged components containing singular (or a very small number of) functions such as resistors, transistors, diodes, etc, lacking any significant integration. For example, is a 16 pin DIP containing 8 50 ohm resistors a "discrete" device, or 8 discrete devices? Fuzzy... I'm sure we don't want to imply we will test a "discrete microprocessor" external to a .4 chip. -------------------------- Def 3.13: In-Circuit testing contains more than just nodal contact (implying observation only) but also stimulus injection into the internal workings of a circuit. Synonyms: "In-Situ test" and "bed-of-nails test". -------------------------- Def 3.15: Change "higher" to "more positive" as in Dot-1. -------------------------- Def 3.19: Change "whose impedance" to "whose DC impedance". -------------------------- Note 1 after Def 3.20: Change "switches depart" to "switches implemented in silicon depart". -------------------------- Note 5 after Def 3.20: This note describes the idea of a "conceptual switch" which is used later as well by that name. Should we have this term brought out into full view? -------------------------- Figure 4 in clause 4.1 refers to "analog boundary cell" in a label rather than "analog boundary module". -------------------------- Clause 4.2 rule permission (c) says the ETAP may contain ANY number of additional analog bus lines. Later in 7.7.2 differential testing with 2 additional lines is discussed, complete with some "how to" info and a nomenclature for the 2 extra lines. In general, how are tools supposed to know what these additional bus lines are for and how they are controlled? If there are no rules to these effects, then anarchy results. My feeling is that we should identify a precise mechanism for handling differential analog busses and limit additional busses to exactly 2. -------------------------- In Clause 4.2, should we mention the "compliance enable" pin concept of 1149.1? -------------------------- Clause 4.3 is about "Controller Outputs". Then a note appears (page 15) that says "all DBMs are required to incorporate the update register". First, this note seems irrelevant to the subject of the clause. Second, why are we imposing a more restrictive rule upon DBMs that are governed by 1149.1? If this rule were followed, I would not be able to use observe-only cells on digital inputs, particularly, clocks. -------------------------- Clause 5, second black bullet: Change "system of test buses" to "system of internal test buses". -------------------------- Clause 5, rule (c) says the test bus interface circuit shall be controlled by a single boundary module. The rest of this clause does not support this rule. -------------------------- Clause 5, rule (d) gives a list of facilities for the AT/AB buses. However, nothing is given to say how these facilities are controlled. This will have to be carefully specified before .4 can be considered "done". -------------------------- Clause 5, rule (d) part (iv): Should "ATEST" be "APROBE"? -------------------------- Clause 5, rule (e) says "AT1 shall be capable of transmitting current...". This brings up an important issue -- how much current? What happens if it cannot transmit the current? Will I know if it cannot? In the design of a current source, you are faced with the problem of a compliance limit which effectively is a limit on the voltage that may be developed by the current source in its attempt to deliver a desired current. This prevents the voltage from going to infinity in the face of an open circuit. If we are interposing switches in the path, we have to explain how this switch will behave when it is unable to transmit the desired current. For example, say we close a switch to a pin, but the pin has open solder to the board. When we apply a current to AT1, no current can flow, but will we know this? What compliance limit do we set on the current source and what voltage may we observe at AT1 or AB1 is the path is broken? -------------------------- Clause 5, rule (e) change: "through a function pin" to "onto AB1 and through a function pin". -------------------------- Clause 5, rule (f) change: "external circuit" to "external circuit onto AB2". -------------------------- Clause 5, recommendation (g) change: "through a function pin" to "onto AB1 and through a function pin". -------------------------- Clause 5, permission (h): says "AT1N and/or AT2N)". Do we really mean "and/or" here? If so, how do we add and control these. As it reads now, this is not clear for the "or" case. -------------------------- Clause 5, permission (i): "ABIST" ?? Where is this defined? -------------------------- Clause 5 figure 6, the figure shows a connection to "DC", but no verbage exists about what this is. -------------------------- Clause 5 Table 1: Mentions "ATEST". Should this be APROBE? -------------------------- Clause 5: This clause does not tell us how the switches are controlled other than to say they are controlled. Are they controlled by flip-flop states? Which states? Where are these flip-flops? Are they part of the Boundary register? If so where? What are their names? (We have lots of examples of switches labeled "S1" elsewhere in the document.) Do they have Update stages responsive to Update-DR? ETC. Of course we have many of these questions answered, but they are not recorded here. -------------------------- Clause 6.1, note after (b): Is this the "single transport" concept from 1149.1? -------------------------- Clause 6.2.1, 2nd paragraph: Says "Each DBM is a logic element contributing a single shift register stage to the boundary-scan register." This is not correct; a DBM may contribute more than one stage for Bidir pins or on pins with extra observe-only cells. Neglecting superfluous observe-only cells, a bidir could be implemented with 1, 2 or 3 cells. -------------------------- Clause 6.2.1 Description, 1st paragraph: Contains the phrase "allows signals to be applied to the core of the integrated circuit without having to pass through the function pins". This phrase is only true for 1149.1 INTEST; for any ABM, we have the problem that we cannot apply any data to any analog input function since we only have two analog buses. In general, I have to object to using INTEST, an 1149.1 term, in any device containing ABMs. It leads the uninformed to wrong conclusions. -------------------------- Clause 6.2.2: Rule (b) includes rule (a), so (a) is redundant. Rule (c) countermands rule (b) and is wrong. Rule (d) in included in (b), so (d) is redundant. Thus we are left simply with rule (b). Permission (e) [I think] is also included in the 1996 revision of 1149.1. -------------------------- Clause 6.2.2 should probably contain words describing how 1149.1 deals with differential signals (in 1996) and how .4 may differ on this point. -------------------------- Clause 6.2.3 rule (c) defines the "core disconnect" feature, which is later shown as a discrete switch. Actually this rule is too strong as worded when you consider inputs; core circuitry connected to inputs should be "unaffected" by applied signals as if disconnected, when the core disconnect function is asserted. This allows a designer discretion in implementation. If, from the outside you cannot discern the actual way the core disconnect was performed, you shouldn't care how it was actually done. I think "core disconnect" should be a proper term in this document because of the implementation implications. -------------------------- Clause 6.2.3.1 says "S1 is the core disconnect facility (Rule 6.2.3(c))" as just mentioned above. Lets bring "core disconnect" more out into the open and also into the definitions of clause 3. -------------------------- Clause 6.2.3.1, after figure 10 has a single sentence saying "...is an optional feature of the revised version of 1149.1", which is not referenced. We need to be clear and consistant on what version we mean. -------------------------- Clause 6.2.3.1, in the paragraphs following Figure 10 discusses an alternative implementation for switches S2 and S3, but doesn't mention the current carrying necessity for these switches. -------------------------- Clause 6.2.3.1, in the third paragraph following Figure 10 discusses how the levels for VH and VL "could be supplied externally". This implies new (and documented) pins for the ETAP if we believe this is so. Ditto for the digitization reference voltage. If it isn't to be done with new pins, then this standard must state how it will be done and how that is controlled. -------------------------- Clause 6.2.3.2 rule (b) implies that the addition of 2 extra analog buses is a prefered implementation. (See above about ANY number of buses.) -------------------------- Clause 6.2.3.2 permission (c) says you can choose the source of voltage levels but doesn't mention current transmission requirements of these sources and switches. It also says the voltage sources can be selectable determined by a control signal AMODE derived from the instruction decoder. However, this begs the questions "What instruction selects the voltage?" which is not answered. -------------------------- Clause 6.2.3.3 deals with the ABM control register. It contains three bits which are unlabeled. To be consistant with 1149.1, to allow layout flexibility, and to clarify this document, they should be labeled and allowed to appear in any shift order within a chain. (Indeed, they could even be mixed up among adjacent ABMs if desired!) In the October minutes, the (corrected) diagram for ABM control used labels X, Y and Z. These are not great labels, but bettern than none. -------------------------- Clause 6.2.3.3 figure 11 is very out of date and inconsistant with the text. This crucial figure badly needs to be updated to avoid confusing readers. For example, it only has 1 mode, where tables and text refer to two. -------------------------- Clause 6.2.3.3 paragraph after figure 11: here it states that DBMs must contain update latches. This is justified by by wanting to avoid shift data rippling on analog circuits, but, is an overkill rule since DBMs feeding digital inputs needn't have these latches. -------------------------- Clause 7.1 rule (c) says "If all instructions are inactive..." which would be better said "When the TAP controller is in the Test-Logic-Reset state..." noting that TLR automatically forces the instruction decoder into BYPASS (or IDCODE when present). -------------------------- Clause 7.1 last paragraph references a "reset*" signal in the (incorrect) figure 11. I don't believe we need a reset* signal when we move to the October 20 '95 design of the ABM control. This saves a globally distributed signal. -------------------------- Clause 7.2, 2nd paragraph, last sentence: Totally baffling. -------------------------- Clause 7.3 talks about "registers that can operate in either system or test mode". If such registers exist, they are user-defined. Yes, they must not affect system function, or it isn't BYPASS, is it. -------------------------- Clause 7.7 talks about INTEST. I do not believe the INTEST paradigm from 1149.1 can be preserved in the presence of ABMs. I suggest we drop it altogether or find a new name. -------------------------- Clause 7.7.1 rule (c) implies that core disconnect must be qualified by an instruction mode signal and by the bits in each ABM control register. If we want this, we need a new figure 11 and table 4 to show how this is to be done. -------------------------- ------------------------------------------------------------------------------