IEEE: Rely on the response and edit from the IEEE editorial
OK: Agree with comment, use additional direction in comment, where provided
Reject: The comment is rejected
"other": Sometimes, edit direction is supplied in this column
|1||Page 3||add Firooz Farhoomand to the list of contributors.||OK|
|2||Page 6||Page references for 9.6 and 9.6.1 are wrong - they should be 108.||OK|
|3||Page 10, Section 1.3.3, first paragraph||"… as illustrated in Figure 3
: to provide for this feature, the standard…"
"Meeting this objective also allows testing…"
Both of these sentences suffer in that the antecedents for "this feature" and "this objective" are not clear.
"… as illustrated in Figure 3: to provide for the testing of components in an extended interconnect, the standard…"
"Designing the device for testing extended interconnects also allows testing…"
|OK: make first change, but not second change|
|4||Page 12, Section 1.3.4||"However, the addition of designer-defined
test functions is in no way…"
poor sentence structure, suggestion:
"The addition of designer-defined test functions is not limited by this standard. The design of the standard allows for the incorporation of ad hoc testability features within the internal core structure."
|OK: "The standard allows…"|
|5||Page 15, Section 3.1.2 and 3.1.10||"a pin on an integrated circuit or other component…" doesn't "other component" include the universe of all components and therefore includes an integrated circuit? Recommendation: "a pin on a component…"||Reject|
|6||Page 17, Section 3.1.12||a test requirement can (imho) be a clarifying note, not a part of the definition. Proposal: change the comma into a full stop and put the second sentence in a note.||OK|
|7||Page 18, Section 3.1.13||This includes reference to compliance-enable pins. This term should be defined. e.g., "compliance-enable pins : a set of one or more pins on a component such that full compliance with the rules of this standard is assured only when a defined pattern of enable signals (a compliance-enable pattern) is applied to the compliance-enable pins. NOTE - There may be more than one compliance-enable pattern."||OK|
|8||Page 18, Section 3.1.14, Note||10 KHz should be 10 kHz||OK|
|9||Page 18, Section 3.1.14||Presently: "KHZ" Change to: "kHZ"||OK|
|10||Page 18, Section 3.1.18||the definition of logic values has a note 3 on the subject of the testing process. (the other notes are clarifying). Note 3 also talks about analog function pins. Although possible, this seems to me distracting from the goal of the definitions. Proposal: leave out note 3. Maybe shift the remark to paragraph 1.3.2||Delete Note 3|
|11||Page 18, Section 3.1.20||Replace "impedance" with "DC impedance" to avoid confusion with characteristic impedance. This should be a simple edit not requiring discussion.||OK|
|12||Page 18, Section 3.1.20||[Purely a matter of English - relative pronouns and all that!] Reword to "an interconnection path between component pins, where the impedance of the path is not significantly different from zero."||OK|
|13||Page 19, Section 3.1.22||Definition does not agree with other parts of the document, and does not cover all cases. Figure 53 shows C1 which is not connected to a function pin; also I think that in figure 53 a residual element could legitimately be connected between nodes N2 and N3, or between N2 and a power supply pin. In each case, the element would not be connected directly to any function pin. Suggest definition is reworded to "a circuit element that is part of a network connected to one or more function pins and that, for operational reasons, cannot be isolated from the pins in test mode. The network of residual elements can be connected to power supply pins as well as to function pins, provided it can be modeled, over a defined working range, by a network of ideal resistors, capacitors, and inductors together with independent D.C. sources."||OK|
|14||Page 21, VG, second sentence||Minor point of English - "the" implies that there is only one pin and one ABM. Would prefer "Any function pin can be connected to VG through its analog boundary module."||OK|
|15||Page 22, Section 4.1.1(a), Note 1||"NOTE -1 " should be "NOTE 1 -" Also, for consistency, "chip" should be replaced by "component".||OK|
|16||Page 22, Section 4.1.1(a), Note 2||Firstly, (for consistency both with dot1 and within this document) these pins should be referred to as "compliance-enable pins" rather than "conformance-enable pins". Secondly, for the sake of completeness, I think we should mention here that there could be multiple compliance-enable patterns. The NOTE could then read: "In accordance with the rules of IEEE Std 1149.1, a component may require the application of a particular pattern of signals (a compliance-enable pattern) to a set of one or more compliance-enable pins before the component is brought into full compliance with this standard. There may be more than one compliance-enable pattern for a particular component."||OK|
|17||Page 22, Section 4.1.1(a), Note 3, Section 188.8.131.52 note, 184.108.40.206 note||Comments regarding a future standard should be omitted from this standard.||Delete Note 3’s last sentence. Change 220.127.116.11 Note from "… is likely to…" to "… may…".|
|18||Page 25, Section 18.104.22.168, Rule (c)||I feel that this rule may explain the state of the all function pins when the TAP controller is in the Test-Logic-Reset. I think that all function pins shall be isolated from the analog test bus AND VH, VL, and(or) VG nodes. Or This may be explained in the 7.3.1. Original Text: "(c) When the TAP controller is in the Test-Logic-Reset state, all function pins shall be isolated from the analog test buses, irrespective of the state of the ABM control register bits." My suggestion: "(c) When the TAP controller is in the Test-Logic-Reset state, all function pins shall be isolated from the analog test buses, VH, VH, and(or) VG nodes in the ABM, irrespective of the state of the ABM control register bits."||Reject|
|19||Page 25, Section 22.214.171.124, Rule (d)||I feel that this rule may explain the state of the all ATAP pins when the TAP controller is in the Test-Logic-Reset. I think that all ATAP pins shall be isolated from the analog test bus AND VH, VL, and Vclamp nodes. Or This may be explained in the 6.2.1. Original Text: "(c) When the TAP controller is in the Test-Logic-Reset state, all ATAP pins shall be isolated from the analog test buses, irrespective of the state of the TBIC control register bits." My suggestion: "(c) When the TAP controller is in the Test-Logic-Reset state, all ATAP pins shall be isolated from the analog test buses, VH, VH, and Vclamp nodes in the TBIC, irrespective of the state of the TBIC control register bits."||Reject|
|20||Page 27, Section 4.4||Figure 8 shows no muxing to the inputs of the test registers. Is that correct? The first paragraph in section 4.4 states: "a common serial data output connected to TDO". A more accurate statement would be "the shift register paths are multiplexed to the common serial data output TDO."||Reject|
|21||Page 27, Last paragraph||I know this is a direct quotation from dot1, but is it correct? Surely the circuitry that delivers the timing is contained within the TAP controller, not in the output stage of the boundary-scan path?||OK: "… circuitry may be required to retime the signal passing through the Output Stage shown in figure 8 to occur…"|
|22||Page 28, Section 5.1.1, Rule (a)||When I read only rule (a), I hesitate that how I treat the other mandatory instructions, BYPASS, SAMPLE/PRELOAD, and EXTEST, though I know that 5.1.2 says about that. Original Text: "(a) Each component shall provide a PROBE instruction.(See 5.3.4)" My suggestion: "(a) Each component shall provide a PROBE instruction in addition to the instructions which mandated in IEEE Std 1149.1."||Reject|
|23||Page 31, Section 126.96.36.199(c)||For consistency, the instruction should be "selected" not "active".||OK|
|24||Page 31, Section 188.8.131.52, Note||I think we should be less firm in our forecast about what dot1 might or might not do. I suggest that the NOTE should be reworded "A future revision of IEEE Std 1149.1 may define SAMPLE and PRELOAD as separate instructions. In this case, the user could effectively re-merge them by using the same instruction code for both."||OK|
|25||Page 32, Section 184.108.40.206, second sentence||This would read better [relative pronouns again!] as "It is also used to test extended interconnect by allowing automatic test equipment (ATE) to make measurements of discrete components connected to the pins."||OK|
|26||Page 32, Section 220.127.116.11||Second paragraph: "to the core, or affect measurements on other pins, or be affected by core signals." Poor grammar, the first "or" after the comma should be removed.||OK|
|27||Page 32, Section 18.104.22.168, last sentence of paragraph 2||EXTEST should be italicized.||OK|
|28||Page 32, last sentence of Note||Not really accurate - dot1 already allows unrestricted choice of code; the new provision would be for all-0s not to be required to produce EXTEST. Suggest this sentence should read "Future revisions of IEEE Std 1149.1 may remove the requirement for all 0s to represent EXTEST."||OK|
|29||Page 32, Section 22.214.171.124(b), (c), (d), (e)||For consistency, the instruction should be "selected" not "active".||OK|
|30||Page 33, Section 126.96.36.199||Line space needed between (c) and (d).||OK|
|31||Page 34, Section 188.8.131.52(c)||Line space needed before NOTE.||OK|
|32||Page 34, Section 184.108.40.206(d), Note||For consistency, the instruction should be "selected" not "active".||OK|
|33||Page 36, Section 220.127.116.11||"Rules (b) to (f)" Where is rule (f)?||Change (f) to (e)|
|34||Page 37, Section 18.104.22.168.1(a), (b), (c)||For consistency, the instruction should be "selected" not "active".||OK|
|35||Page 37, Section 22.214.171.124.2||"This instruction will then be loaded into the instruction register on the falling edge…" Poor grammar, which instruction is "this instruction". The word "then" is unnecessary. Recommendation: "The IDCODE instruction will be loaded into the instruction register on the falling edge…"||Reject|
|36||Page 38, Section 126.96.36.199.1(a), (b), (c)||For consistency, the instruction should be "selected" not "active".||OK|
|37||Page 38, Section 188.8.131.52.2||the last sentence "This code will … through TDO" This describes a proposed behavior by an implementation. I will bring this as a comment to the .1 working group as well. Proposal: change the word "identification" to "selected data" (only if we can deviate from the .1 std on this one, otherwise leave it as it was…)||Reject|
|38||Page 38, Section 184.108.40.206, Rule (a)||Define what a "self-contained" instruction is in the context of device and tester resource requirements.||Reject|
|39||Page 40, Section 220.127.116.11, last line||Would be more accurate to say "(This data can be previously inserted, e.g. by using the PRELOAD phase of the SAMPLE/PRELOAD instruction.)"||OK|
|40||Page 40, Section 18.104.22.168(a)||This rule should apply only to output pins (as it does in dot1). "analog function pins" should be replaced by "analog function output pins" (or just "analog output pins").||Reject|
|41||Page 40, Section 22.214.171.124||There should be a rule to say what happens at analog input pins (c.f. dot1 7.14.1(c)). Suggest "When the HIGHZ instruction is selected, all analog input pins shall be isolated from all test circuitry, and, if possible, from the core (i.e., all switches in the ABM, including the CD switch if any, shall be open). NOTE - If some or all of the input pins are not provided with CD switches, the core circuitry shall be controlled so that it cannot be damaged as a result of signals received at the input pins."||Reject|
|42||Page 40, Section 126.96.36.199(b)||Cross-reference is wrong - it should be 6.2.||OK|
|43||Page 40, Section 188.8.131.52||Additional comments would be helpful to explain (b). Suggest adding "The ATAP pins are also isolated from the internal test bus lines (see NOTE 2 of Table 2)."||OK|
|44||Page 42, Section 6.2.1 (g)||The use of the word "derived" is not precise. Suggest using "supplied".||Reject|
|45||Page 43, Section 6.2.2||Presently: "Figure 2, page 9" Change to: "Figure 2, page 10"||Delete page ref|
|46||Page 43, Section 6.2.2, line 5||Figure 2 is on page 10.||Delete page ref|
|47||Page 44, last line of paragraph 4||Recommendation 6.2(o) should read 6.2.1(o)||OK|
|48||Page 45, Section 6.2.2, first paragraph||"It also allows the voltage appearing…" What does "it" refer to? Recommendation: "The TBIC architecture also allows the voltage appearing…"||OK: "The switching structure also allows…"|
|49||Page 45, line immediately above figure 15||"a" should be inserted at the beginning of the line.||OK|
|50||Page 45, sixth line from the bottom||Recommendation 6.2(o) should read 6.2.1(o)||OK|
|51||Page 45, last paragraph||Recommendation 6.2(o) should read 6.2.1(o). Also, this condition is also used in many other instructions. Suggest changing the last sentence to "It also provides the high-Z condition that is always needed for BYPASS, SAMPLE/PRELOAD, HIGHZ, IDCODE, and USERCODE, and that can be used in other instructions."||OK: no "always"|
|52||Page 48, Section 6.3, line 1||"6.2" should read "6.2.1"||OK|
|53||Page 48, Rule 6.3.1(e)||probably fails the "black box" test. Why do we say that it has 4 stages? It may actually be composed of 10 stages on the output of the control logic in Figure 14. I could not determine this from the I/O pins of the device. (Why I didn't see this problem long ago, I don't know.) It's not severe, but Benoit will undoubtedly see it.||OK: "The update register
shall be parallel loaded from the control register…"
|54||Page 50||Presently: "responsibilty" Change to: "responsibility"||OK|
|55||Pages 50-51, control logic equations||There was at least one comment
in the first ballot indicating that the reader was not clear as to where
these equations came from. When I came to check the equations, I realized
that it was not entirely obvious! We could insert a few words of explanation,
if the WG thought it worth while. It might go something like this, starting
immediately after table 3, and finishing immediately before the set of
equations on Page 51.
"The detailed design of the TBIC requires that versions of Tables 1, 2, and 3 must first be prepared, taking into account the instructions that are to be supported (i.e., mandatory + optional + user-defined). Table 1 could include additional switching patterns for user-defined purposes; Table 2 could include additional columns (for user-defined instructions) and/or could use different codings to select the patterns; Table 3 could need additional mode signals to identify instructions and/or could code them differently.
To design the control logic needed (see figure 14) to control a particular switch, it is necessary to identify (from Table 1) which patterns require that switch to be closed. Table 2 then shows which codings under which instructions select those patterns, and Table 3 shows the appropriate mode signals that identify the instructions.
The procedure can be illustrated using the tables as they are (i.e., implementing a TBIC for a component supporting all defined instructions (mandatory and optional) but no user-defined instructions) and finding the logic to drive switch S5. Note that in the equations the control signal for switch SN is denoted by SN, and that the code and mode bits are denoted by CALIBRATE = Ca; CONTROL = Co; DATA1 = D1; DATA2 = D2; Mode1 = M1; Mode2 = M2.
1. From Table 1 we find that S5 is required to be closed for P2, P3, and P9.
2. From Table 2 we find that P2 is required in EXTEST, CLAMP, RUNBIST, PROBE, and INTEST for code Ca.Co.D1.D2 = 0010; P3 is required in EXTEST, CLAMP, RUNBIST, PROBE, and INTEST for code Ca.Co.D1.D2 = 0011; and P9 is required in EXTEST, CLAMP, and RUNBIST for code Ca.Co.D1.D2 = 1010.
3. From Table 3 we find that the group of instructions EXTEST, CLAMP, and RUNBIST is represented by M1.M2 = 11, and that the group PROBE and INTEST is represented by M1.M2 = 01.
4. Putting these together we then get
S5 = /Ca./Co.D1./D2.M1.M2
which can be simplified to
S5 = /Co.D1.M2 (/Ca + /D2.M1)
The full set of logic equations for the control logic in figure 14 then becomes"
|56||Page 51||Presently: "3-state" Change to: "three-state" To be consistent with pages 65, 66||Use "3-state"|
|57||Page 52, Section 6.4.2, paragraph 2||"clause 7.4" should read "7.4" [IEEE style]||Reject|
|58||Page 53, Section 184.108.40.206(a), Note||"6.2(o)" should read "6.2.1(o)"||OK|
|59||Page 53, Section 220.127.116.11(b)||"6.2" should read "6.2.1"||OK|
|60||Page 56, Section 18.104.22.168, paragraph 1||"6.3" should be "6.3.2"||OK|
|61||Page 56, Section 22.214.171.124, paragraph 2||add to end of sentence "… equations, derived from tables 4 and 5 in the same way as the equations in 6.3.2."||OK|
|62||Page 56, Figure 16||Presently: Co line is drawn differently than Ca line. Change to: Co line should be drawn like Ca line, dashed to right side||OK|
|63||Page 61, Section 7.2.2, (i)||"… from a pair is used to drive a "conventional" input pin…" Define "conventional" pin. Should "conventional" be replaced with "single ended"?||OK: use "single ended"|
|64||Page 61||Presently: "(as illustrated in Figure 4 page 11)" Delete, because Fig 4 is not an example of an optional DBM||OK|
|65||Pages 62-82||Throughout this clause, voltages (VH, VL, etc) referred to in the text are often (but not invariably) italicized. In the rest of the document (including the definitions clause) they are not. For consistency, therefore, the italics should be removed from this clause (37 instances).||IEEE|
|66||Page 62, Section 7.3.1, Rule b||Presently: "An ABM attached to an output pin shall be designed with a "core disconnect" facility." Change to: "An ABM attached to a pin shall…" This rule should apply to both inputs and outputs, even though the core disconnect switch may be conceptual in the case of an input pin. This is a case of 'behaves as if'.||OK|
|67||Page 63, Section 7.3.1, Recommendation j||Presently: "An ABM attached to an input pin should be designed with a "core disconnect" facility." Delete the rule, and modify Rule (b) as proposed earlier. Otherwise there is no rule requiring input pins to be suitably disconnected from the core during measurements.||Reject: [covered by Rule, save deletion for later draft]|
|68||Page 66, Section 126.96.36.199||The rules relating to residual
elements do not seem to cover all the cases. We can have residual elements
that are not connected to any function pin; we can have a residual element
connected to a digital function pin (e.g., a termination resistor on a
digital bus driver). There is also an inconsistency, in that (a) says that
residual elements are linear two-terminal elements, and (f) says they are
not necessarily like that. I don't in any case like the wording of (f)
- an element cannot consist of a network; a network contains elements!
Finally, I wonder what "devices" are envisaged in (f)? It seems to me that
the only one that could satisfy (a) is a diode - a transistor model contains
a dependent source. I suggest the following set of rules: "Rules
(a) If any circuitry cannot be isolated from the function pins in test mode, it shall be capable of being modeled as a network of residual elements.
(b) Residual elements shall consist exclusively of linear passive components (resistors, capacitors, and inductors) together with independent D.C. voltage and current sources.
(c) If one end of a residual element is connected to an analog function pin, the other end shall be connected either to another analog function pin, or to a power supply pin, or to other residual elements.
NOTE - Reference supply pins are considered to be analog function pins.
(d) If one end of a residual element is connected to a digital function pin, the other end shall be connected to a power supply pin.
(e) Residual elements shall not connect to the core circuitry.
(f) All residual elements must be documented.
NOTE - The documentation required for residual elements is detailed in clause 10, which also specifies the way in which it must be presented.
(g) The use of residual elements should be avoided as far as possible without compromising mission function or performance.
(h) The residual element network may contain networks or devices whose model in terms of linear networks (as in 188.8.131.52(b) above) is valid only over a specified range of pin currents and voltages."
|OK: remove (d), leave (e) as old D25’s (c) was worded|
|69||Page 67, Figure 22||It doesn't really matter, but E4 and E5 are simply in parallel. Perhaps E5 should be connected to a power supply pin. And if we are making changes, perhaps an element could be connected between F4 and a power supply pin. It might also be worth while to put a large cross over the disallowed elements (E6 and E7) so that the customers are in no doubt.||Leave E5; add "X" over E6, E7|
|70||Page 68||If figure 22 is changed, there will be consequential changes to the description.||Reject|
|71||Page 71, Table 8||The caption of this table should make it clear that this is only an example set of switching patterns. Suggest "Switching requirements for example ABM (figure 23)"||OK|
|72||Page 72, Section 184.108.40.206(e)||As written, this rule seems too restrictive. Table 8 specifies codings, supports all optional defined instructions, and makes no provision for user-defined instructions. In short, it is a specific implementation, which was not intended to be prescriptive. I think this rule should be deleted.||Change wording to stipulate only mandatory behaviors defined in rules of Standard. Save major "behavioral" edit for later draft.|
|73||Page 74, equations||I do not agree with three of the equations. I hope that others will derive these independently and confirm the correct values. I think we should have [NOT K represented by /K] SD = /M1(/M2 + /C./D) SB1 = B1.M2(M1 + /C./D) SB2 = B2.M2(M1 + /C./D) The others, I think, are correct.||Reject|
|74||Page 74, Section 7.4.1(b), Note 1||Same as 6.3.1(e), fails the black box test.||OK: Delete "four-bit" twice.|
|75||Page 77, Section 7.4.1(l)||redundant full stop to be removed.||OK|
|76||Page 77, permission (l)||Delete second '.' at end of sentence.||OK|
|77||Page 77, Section 7.4.2||"This is summarised in Table 10…" Use the U.S. spelling "summarized"||OK|
|78||Pages 78-79, Figures 24 and 25||For consistency, either there should be inversion bubbles on both differential amplifiers or on neither of them.||OK|
|79||Page 78, Section 7.4.2||"the manufacturer is recommended, but not obliged, to document it)." The word recommended is not a good choice for this sentence, perhaps "encouraged" would be more appropriate.||Reject|
|80||Page 79, second paragraph||remove inverted commas round "analog"||Reject|
|81||Page 79, Section 7.4.2||"To ensure a valid logic state is always captured, the differential signal is also compared with a zero-offset differential digitizing receiver or comparator, to be captured by the BUS1 bit of the non-inverting control register." This statement should have a figure to illustrate the concept.||Add labels to Figures 24, 25: "differential digitizing receiver" on rightmost amplifier symbol|
|82||Page 79, Section 7.4.2||"Though not shown in Figure 24, the AB1 and AB2 connections from the differential ABM may instead be connected to the optional internal differential lines AB1N and AB2N…" Figure 25 shows two sets of AB1 and AB2 lines (one set for inverting pin and one set for non-inverting pin). The statement is unclear. Suggestion: "Though not shown in Figure 24, the AB1 and AB2 connections on the inverting pin of the differential ABM may instead be connected to the optional internal differential lines AB1N and AB2N…"||OK|
|83||Page 81, First sentence of paragraph 3||should read "... switches are enabled."||OK|
|84||Page 81, Last sentence of paragraph 3||Should read "… excursions that a pair…"||OK|
|85||Page 83, Section 8.1.1, third line from bottom||instruction should be "selected" rather than "active" (twice)||OK|
|86||Page 83, Section 8.1.1, last paragraph||Figure 2 is on page 10.||Delete page ref|
|87||Page 83, Section 8.1.1||last paragraph (see figure 2 on page 9) should be page 10.||Delete page ref|
|88||Page 85, Section 8.1.2, last paragraph||The first sentence reads rather strangely! Suggest changing to "All required differential outputs should be provided by the normal system driver, just as in the single-ended case."||OK|
|89||Pages 87-93||Symbols in text (e.g., IT, VG etc) should be de-italicized for consistency. (11 instances)||OK|
|90||Page 88, Section 8.2.2||"For the first measurement, illustrated in Figure 33…" The node being measured for the first measurement is not stated. Suggestion: "The first measurement, the measurement of the voltage at Vf1, is illustrated in Figure 33. A current stimulus…"||OK|
|91||Page 95, second paragraph||The switches are called SG, SH, SL (6 instances)||OK|
|92||Page 96, Section 9.3.2, second paragraph||The switches are called SG, SH, SL, SB1, SB2 (5 instances)||OK|
|93||Page 97, Section 9.4(a), Note||There is no S5 in figure 50 - reference should be to figure 42.||OK|
|94||Page 97, Section 9.4(b) Note||There is no S6 in figure 50 - reference should be to figure 43.||OK|
|95||Page 97, Figure 39(a)||Presently: "PIN" Change to: "PAD". This diagram shows how to connect to a pad, not a pin.||Leave figure, but change page 96, section 9.3.2, 2nd paragraph, last sentence "pad" to "pin" (twice).|
|96||Page 97, Figure 39(b)||Presently: A pad is located at juncture of Rcom and Rs Change to: delete the pad because it could be anywhere along Rcom||Reject|
|97||Page 97, Rule (a), Note||change "figure 50" to "figure 42"||OK|
|98||Page 97, Rule (b), Note||change "figure 50" to "figure 43"||OK|
|99||Page 98, Rule (f)(i)||this description results in a question mark with the designers. A bias of Vdd or Vss and then add a 100mV sine wave … will clip … No implementation will monitor a sinewave correctly with such a bias, without additional 'helper voltages'. (this is obviously not what we mean to say, or might be read from this rule) Proposal: ?||Reject|
|100||Page 98, Section 9.4 Rule(g) and Rule(h)||The specifications for the voltmeter are not appropriate for the measurement of a 1kHz sinusoid. If the voltmeter has a *3dB bandwidth at 1.001kHz, for example, the measurement error for a signal at 1kHz will most certainly be greater than 1%.||Change Voltmeter bandwidth to 10KHz|
|101||Page 99, Section 9.4j||Presently: "small impedances" Change to: "large impedances". Coupling between AT1 and AT2 makes it more difficult to measure high resistances, and small capacitances, which are grouped using the term 'large' impedances.||Reject|
|102||Page 99, Section 9.4, Recommendation (m)||The statement "(implying a *3dB bandwidth of 100 kHz for a first order, low pass filter)" implies knowledge about the output characteristics of the driver and the characteristics of the load and is therefore purely conjecture. This statement should be eliminated.||Add wording: ", for example"|
|103||Page 102, Section 9.5.1||Delete "it may be adjusted to provide the desired voltage amplitude at the AT1 pin." This phrase suggests that Rm is the means by which the AT1 voltage is adjusted. Typically, Rm will have a constant value for all measurements, and only the voltage source amplitude will be adjusted.||Change to: "… it is selected to provide an adequate differential voltage measurement to infer the current into the AT1 pin."|
|104||Page 104, Section 220.127.116.11||switches named as "SAB1" should be "SB1" (twice)||"SAB1" to "SB1"|
|105||Page 104, Section 18.104.22.168||There is no switch labeled SAB1 in figure 33. Should the switch name be SB2?||"SAB1" to "SB1"|
|106||Page 104, Section 22.214.171.124, Rule 9.4(d), description||Presently: "SAB1, S6, and SG" Change to: "S5, SB1, and SG"||OK|
|107||Page 104, Section 126.96.36.199, Rule 9.4(d), description||Presently: "SAB1 and S6" Change to: "S5 and SB1"||OK|
|108||Page 105, Figure 45||does not show any measurement. (the surrounding figures do). Proposal: Add the measurement device in the drawing (volt meter).||OK|
|109||Page 107, penultimate line||Figure 35 is on page 90||Delete page ref|
|110||Page 107, Figure 48||Add labels to the switches, just to be consistent with other figures.||OK|
|111||Page 107, second last line||Presently: "Figure 35 (page 89)" Change to: "Figure 35 (page 90)"||Delete page ref|
|112||Page 107, last line but one||(page 89) change to (page 90).||Delete page ref|
|113||Page 108, third and fourth lines||Presently: "kohm" … "uA" Change to: "k[omega]" … "[mu]A". Use Greek letters to be consistent with rest of document.||OK|
|114||Page 108||Presently: "3-state" Change to: "three-state". To be consistent with pages 65, 66||Use "3-state"|
|115||Page 108, third line||"1 kohm" should use omega symbol||OK|
|116||Page 108, Third paragraph||The first line reads strangely : Test-Logic-Reset is a TAP controller state, BYPASS and High-Z are instructions, and none of them are modes! I am not sure what the correction should be, but something surely needs to be changed!||Change wording to "AT1 and AT2 may be left floating in some circumstances. This can occur when all the 1149.4-compliant components are in Test-Logic-Reset state, during normal operation. It can also occur when all the components are executing BYPASS or HIGHZ instructions, have disconnected TBICs in their boundary register programming, or have connected TBICs but no connected ABMs. If the AT1 and AT2 buses are left floating, however, this may result in noise coupling between components or susceptibility to ESD."|
|117||Page 113, Section 10.1.1(a), Note 2||line 2 : for "are" read "is" line 3 : insert hyphen between "compliance" and "enable"||OK|
|118||Page 113, Section 10.1.1(a)||Additional NOTE to say "There may be more than one compliance-enable pattern that will enable compliance with this standard."||OK|
|119||Page 114, Figure 52||Presently: Polarity of Voffset is opposite to that in Figs 44, 45 Change to: Reverse polarity of Voffset||OK|
|120||Page 114, Note||Presently: "If one of these values" Change to: "If one of these voltage values". To make it clear that the note only applies to point (5).||OK|
|121||Page 115, 116||Presently: "3. 0 volts - 0 volts
0 amps - 0 amps
0 volts - 3.5 volts"
Change to: "3. 0 - 0 volts
0 - 0 amps
0 - 3.5 volts"
I misread the present numbers several times before realizing that it was not 4.0 amps! Please insert extra spaces between the number/bullets and the text. Also, we don't need to put the units twice in each line.
|122||Page 115, 116, the 10 parameter example||Just make a table from it like is done with table 12.||Reformat as 121 (IEEE)|
|123||Page 116, Table||has no heading. Add "Table 12" here, and change "Table 12" to "Table 13".||Reject (IEEE)|
|124||Page 117, Rule (e)(i) and Rule (f)(i)||change the word "construction" to "behavior". I think we cannot ask for an implementation. A standardized behavior is what we need. How it is done may be the designer's IP.||OK: use "behavioral model"|
|125||Page 117, Section 10.2.2||Delete rule (e)(v) because it is redundant w.r.t. (e)(iv). If it is decided that it is not redundant, then add a rule for AT1 as well.||Delete (e)(v)|
|126||Page 118, Section 10.3.1(a)||To be consistent with earlier definitions and descriptions of the residual element problem, suggest that the rule be rewritten as follows. "Any circuit network that remains connected to the function pins when the component is in CD mode shall be modeled as a network of residual elements and described in a Residual Element Table."||OK|
|127||Page 120, Figure 53||Presently: pin numbers F1,2,3,3,5,1,2,4 Change to: F1,2,3,4,5,6,7,8||OK|
|128||Page 120, Figure 53, Examples of residual elements||Function pins should be numbered from top left to bottom left: "F1, F2, F3, F4" [instead of "F1, F2, F3, F3"] and from top right to bottom right: "F5, F6, F7, F8" [instead of "F5, F1, F2, F4"]||OK|
|129||Page 121, Table 12||Residual element table for the components shown in Figure 53 The last entry should be: "(ABM) N3 F8" [instead of "(ABM) N1 F4"] The text that describes the Figure and Table refers to the corrected pin numbers and node.||OK|
|130||Page 121, Table 12, last line||Presently: "N1 F4" Change to: "N3 F8"||OK|
|131||Page 121, Table 12, Note 2||Remove redundant full stop.||OK|
|132||Figures 1, 18, 22, 24, 25, 26, 34, 35, 43, 44, 45, 46, 47, 48, 49, 52, 53, Tables 6, 10, 11, 12||add a ":" after Figure/Table number.||OK|
|133||General||Many areas of the document refer to other sections. One example is on the top of page 25 with the statement "as defined in 7.3.5". Many technical documents would describe what 7.3.5 is. Examples: "as defined in section 7.3.5", "as defined in clause 7.3.5", "as shown in figure 6", etc. The convention I describe was used several places in the document but it was not used consistently throughout the document.||IEEE (and then capitalize per comment 142)|
|134||General||Some future test applications may involve the verification of resistive and reactive components in a network using 1149.4. The current techniques involve the use of quadrature measurements where the amplitude and phase of a signal are determined. If these techniques are used with 1149.4 devices, the level of phase distortion presented by the switches or buffers must be disclosed by the manufacturer or characterized as part of the board level test. Either way, limits to the amount of phase distortion offered by the 1149.4 analog structures must be determined and added to the standard.||Reject|
|135||General||Only first- and second-level heads will be listed in the Table of Contents||IEEE|
|136||General||Would you like users to refer to the most recent version of the standards in Clause 2? If so, the statement preceding the lists of references should read, "This standard shall be used in conjunction with the following publications. When the following standards are superseded by an approved revision, the revision shall apply."||Reject|
|137||General||References (Clause 2) should be listed in alphanumeric order. When calling them out in text, use the standards designation and year, e.g., see IEEE Std C37.23-1998. The title of the standard should only be written out in Clause 2.||IEEE|
|138||General||It may be preferable to use a footnote instead of a Note for the information in Clause 2 concerning IEEE Std 1149.1a and 1149.1b.||Reject (IEEE)|
|139||General||The following statement should precede the list of terms and definitions (3.1.1): "For the purposes of this standard, the following terms and definitions apply. IEEE Std 100-1996 should be referenced for terms not defined in this clause."||OK|
|140||General||Our style is to use ac and dc rather than A.C. and D.C., or a.c. and d.c.||OK|
|141||General||Should the title of 4.1.1, 188.8.131.52, etc. be "Specification rules"?||Reject (IEEE)|
|142||General||Major clauses should be referenced using an initial capital letter for "Clause," e.g., Clause 2.||IEEE|
|143||General||When citing figures, do not give page references, i.e., use "see Figure 1 and Figure 2" instead of "see Figure 1, page 8, and Figure 2, page 9."||Delete page ref|
|144||General||The format of all lists needs to be changed to the outline format given in the Style Manual in 11.2. Ordered lists "should be presented in outline form, with items lettered a), b), c), etc. If further subdivision of the items is necessary, 1), 2), 3); I), ii), iii); etc., should be used to form a tiered list."||IEEE|
|145||General||The format of equations is
E = mc2 (1)
E is energy,
Note that all variables should be italicized (including points on lines and variables that represent constants) while constants remain roman. Please check equations to ensure that variables are identified correctly.
|146||General||Use abbreviations of units after numbers, e.g., use "1 h" instead of "1 hour" or "one hour." A space should precede all abbreviated units (except %). This includes A, V, m C, and m F.||IEEE|
|147||General||The Working Group will need to provide clean reproducible-quality figures in electronic format (preferably TIFF or EPS format).||OK|
|148||Page 120, Figure 53||Examples of residual elements Function pins should be numbered from top left to bottom left: "F1, F2, F3, F4" [instead of "F1, F2, F3, F3"] and from top right to bottom right: "F5, F6, F7, F8" [instead of "F5, F1, F2, F4"]||OK|
|149||Table 121, Table 12||Residual element table for the components shown in Figure 53 The last entry should be: "(ABM) N3 F8" [instead of "(ABM) N1 F4"]||OK|