P1149.4 subgroup meeting - 18 July 1995 at IMP 
Attendees: Keith Lofstrom, Steve Dollens, R. Dandapani, Mani Soma 
 
Goals of the meeting: 
have a clearly defined test plan to accompany the test chip and 
  demonstration board 
assign work to the appropriate people to implement the test plan 
write the documents for distribution 
 
Action items: 
The specific work is described in more details below. This is the list 
  of action items: 
BSDL for the test chip and the demo board: Ken Parker. To coordinate 
  with Keith Lofstrom and Al Heiden.  
Input is the logic design of the controller from Keith 
Output is the test vector file for the structural integrity test of the 
  controller, test vector file for appropriate instructions to set the 
  switches. These test vector files will be used by Keith and Al in their 
  test and further work. 
Software driver from PC to the parallel port on the demo board: Keith 
  Lofstrom. 
Design and manufacturing of the demo board: Steve Dollens. To 
  incorporate: 
  two P1149.4 test chips,  
  one commercial 1149.1 chip, 
  a parallel port for PC communication, 
  2  high bandwidth I/O connections, 
  one simple wire between 2 pins on the 1149.1 chip, 
  one simple wire between 2 pins on the P1149.4 chips, 
  one complex wire between 2 pins on the P1149.4 chips, 
  one simple wire between the 1149.1 chip and a P1149.1 chip, 
  an open area for people to add their own components. 
Simplified block diagram of the P1149.4 chip used for test purposes: 
  Keith Lofstrom. 
Execution of test plan before releasing boards to users: Al Heiden. 
Menu software for the demo board: Steve Dollens and Mani Soma. Steve to 
  provide the basic software available from IMP, Mani Soma to work with 
  Keith to customize the software to show the customer the capabilities of 
  the P1149.4 test bus using the demo board. 
Test document distribution via the web: Mani Soma. 
Test chip, demo board, and software distribution: Steve Dollens. 
Possible to ftp for software distribution via the web site at UW. 
Generation of test documents: no specific assignment to a person. Each 
  person with action items needs to produce documents to send to Mani 
  Soma. 
Feedback from users of the demo board on the web: Mani Soma. 
 
Technical points discussed: 
Fabrication scheduled for July. Quick design review at IMP. Chips 
  available end of August, demo boards available two weeks later. 
Vmin / Vmax are defined by the application electronics and are global 
  per chip (two chips can have different Vmin and Vmax). 
Default state for mission electronics: all switches, except Core 
Disconnect, are open. 
Power-up initialization: see what 1149.1 does. Initialize to Vmin? Need 
  to provide a clear description of the default power-up state for the 
  P1149.4 chips. 
Board might run up to 30 Mhz due to interconnect parasitics, even though 
  on-chip differential amplifier is designed for 100 Mhz. 
Initialization before entering test mode: need to clarify the default or 
  reset state before entering the interconnect test mode. Or leave all 
  states undefined until a test instruction is executed. Check possible 
  charge storage at passive components, 50-ohm loads, etc. before 
  connecting Vmin, Vmax. 
Structural integrity test of the test bus facilities (using BSDL): 
  verify the controller integrity (1149.1 TAP extended with status 
  registers, early capture, instruction decoder, etc. specific for this 
  test chip only). 
check all 1149.1 scan cells, bypassing all 1149.4 chips. 
check all P1149.4 scan cells and switches (possibly by connecting AT1 
and AT2 to the same pin simultaneously, etc.), bypassing the 1149.1 
  chip. 
check all 1149.1 and P1149.4 scan cells and switches simultaneously. 
EXTEST demo for the simple wire between two 1149.1 pins. BSDL. 
EXTEST demo for the simple wire between two P1149.4 pins. BSDL. 
EXTEST demo for the simple wire between a 1149.1 pin and a P1149.4 pin. 
BSDL. 
EXTEST demo for the complex wire betwen two P1149.4 pins. BSDL. 
Termination of test mode: reset to Vmin? Check default state to end the 
  test mode before returning to normal operation. 
Testing other optional features of P1149.4: early capture, in-test, etc. 
  (not required as part of the test plan and document). 
Test mission electronics: differential amplifier (normal, no P1149.4 
  cell) and differential amplifier (with full P1149.4 cells).