JTAG Analog Extension

Test Chip

Target Specification

for the

IEEE P1149.4 Working Group

02/19/98

Preliminary Rev 0.12

 

The Analog Test Chip will allow members of the IEEE P1149.4 committee to evaluate the various switch structures proposed for the IEEE P1149.4 analog test standard. The chip will contain the following:

 

5 pin JTAG compatible tap (TCK, TMS, TDI, TDO, and RSTB).

AT1 and AT2 analog test ports

AT3 and AT4 analog test ports for differential testing

Core Disconnect output.

Four different styles of boundary cells for testing.

A differential amplifier with 4-bus testing.

Separate "test VH" and "test VL" pads for the pseudo-1149.1 switches.

Analog Comparators on some boundary cells

Early Capture extension for speed testing

On chip process monitors - FET diodes and VT measurement cells

Analog TMS experimental option

 

1.1 Purpose of the Study

This test chip will allow benchtop and tester evaluation of proposed features for the IEEE P1149.4 Analog Test Standard. It will also force a reality check on what we expect to do with the standard.

With a real integrated circuit, we should be able to demonstrate the utility of analog scan testing, and show test engineers and designers of both chips and systems the small cost and testing benefits of this technology.

In addition, KLIC has added some optional features extending the standard for waveform extraction. These optional features will allow test engineers and designers to extract waveforms and perform timing measurements on P1149.4 chips, offering potential users more reasons to embrace the standard.

KLIC also has included some internal probe points, to demonstrate the feasibility of internal probing of circuits, as well as the possibility that test key interconnect may be performed via the P1149.4 interface. By incorporating test keys into the P1149.4 structure, we can save wafer real estate, minimizing or even negating the cost of adding P1149.4 to devices.

2.1 Block Diagram

2.2 Chip Plan

2.3 Pinout Table

Pin

Number

Name

Description

1

Compare

Analog Compare Level

2

VH

Vmax voltage for boundary interconnect testing

3

VL

Vmin voltage for boundary interconnect testing

4

DVDD

Digital VDD power supply

5

DVSS

Digital VSS power supply

6

DOUT

1149.1 boundary cell test output

7

DIN

1149.1 boundary cell test input

8

RSTB

JTAG (and chip) reset

9

TMS

JTAG test mode select

10

TDI

JTAG test data input

11

TCK

JTAG test clock

12

TDO

JTAG test data output

13

CD

Core Disconnect logic output

14

DVSS

Digital VSS power supply

15

DVDD

Digital VDD power supply

16

ATMS

Analog TMS experimental switch to AT1

17

AVDD

Amplifier Analog VDD power supply

18

AINL

Amplifier Inverting Input

19

AINH

Amplifier Non-Inverting Input

20

AOUTL

Amplifier Inverting Output

21

AOUTH

Amplifier Non-Inverting Output

22

BOUTH

Amplifier with boundary cell, Non-Inverting Output

23

BOUTL

Amplifier with boundary cell, Inverting Output

24

BINH

Amplifier with boundary cell, Non-Inverting Input

25

BINL

Amplifier with boundary cell, Inverting Input

26

AVSS

Amplifier Analog VSS power supply

27

BC4P

BC4 test boundary cell, pad side connection

28

BC4C

BC4 test boundary cell, core side connection

29

BC3P

BC3 test boundary cell, pad side connection

30

BC3C

BC3 test boundary cell, core side connection

31

BC2P

BC2 test boundary cell, pad side connection

32

BC2C

BC2 test boundary cell, core side connection

33

BC1P

BC1 test boundary cell, pad side connection

34

BC1C

BC1 test boundary cell, core side connection

35

BC0P

BC0 test boundary cell, pad side connection

36

BC0C

BC0 test boundary cell, core side connection

37

AT1

AT1 Stimulus input

38

AT2

AT2 Measurement output

39

AT3

AT3 Stimulus input

40

AT4

AT4 Measurement output

NOTE: Package pin number will depend on the package used. The pins will be in the same sequence as shown.

Package Pinout 40 pin 0.6inch 100mil DIP

2.4 JTAG Register Model

The register model shows the standard instruction, boundary, and bypass registers, as well as an additional Control/Status Register.

When the chip is reset, either by the TRST pin, the "5-TMS" reset, or by a reset instruction, all update registers in the boundary register and all control/status update registers are reset to zero.

2.5 JTAG Instruction Set

There has been much discussion about the form the instructions want to take. Rather than tie functions together in a few instructions, the test chip has been implemented to allow a great deal of flexibility in choosing which control lines are driven together. In a real chip, we will probably let MODE == AMODE == PMODE, for example - here they are independently controlled. This flexibility allows users to try various combinations of functions.

Instruction Register Decoding

Binary

7654 32 10

Instruction

Data Register

Lines Asserted

0000 0000

EXTEST

Boundary

MODE, AMODE, PMODE, CD

0001 1110

SAMPLE/PRELOAD

Boundary

 

01xx xxxx

Control/STATUS Register

Status

 

10xx xxxx

Modified BYPASS

Bypass

 

eexx xxx1

Analog TMS switch enabled

Boundary

ATMSenab

eexx xx0x

Analog Test switches enabled

-

AMODE

eexx x0xx

Assert MODE

MODE

eexx 0xxx

Pseudo .1 switches enabled

PMODE

eex0 xxxx

Core Disconnect

CD

ee1x xxxx

Early Capture

EC

11xx 10xx

RESET Instruction

Bypass

RESET

11xx xx11

ID Instruction (not impl.)

Bypass

 

1111 1111

11xx xxx1

BYPASS

Bypass

 

ee = 00, 01, 10, but not 11

The JTAG Instruction register for the P1149.4 test chip is an 8 bit register, with readback. The basic instructions are EXTEST, SAMPLE, STATUS, RESET, and BYPASS. The first three instructions are modified by bits 0, 1, 2, 3, 4, and 5 of the instruction, to enable the control lines ATMS, AMODE, MODE, PMODE and CD, as well as set the EC or Early Capture control bit. Notice that the mode bits are set by logic 0; this simplifies the decoding logic for the EXTEST instruction.

The modification bits are asserted if bit 7 or 6 is zero. This allows the boundary register outputs and Core Disconnect to remain asserted even when we are talking to the Status or Bypass Register.

The EC bit is a transparent addition to the normal JTAG cycle, allowing a CAPTURE event to occur simultaneously or just after UPDATE changes the outputs, rather than waiting 2.5 clock cycles for a normal capture. This will be described in greater detail in another section.

2.6 Control/Status Register

The 4 bit Control/Status register allows us to control various bias lines and observe various conditions on the test chip. For this version of the chip, we have only one control bit and no status bits:

Bit 0 Amplifier Direct Enable

Bit 1 Amplifier Disable if CD

2.7 Boundary Register Order

The Boundary register is made up of the following cell groups, ordered from TDI to TDO:

Cell

Type

# of

Bits

# of Pads

Notes

D.I

Digital 1149.1 Enhanced Input Cell

1

1

D

D.O

Digital 1149.1 Enhanced Output Cell

2

1

D

B.AB4

AT4 boundary switch

3

1

A,D

B.AB3

AT3 boundary switch

3

1

A,D

B.AB2

AT2 boundary switch

3

1

A,D

B.AB1

AT1 boundary switch

3

1

A,D

I.ND

NFET diode internal probe

1

0

 

I.NV

NFET threshold measurement internal probe

1

0

 

I.PD

PFET diode internal probe

1

0

 

I.PV

PFET threshold measurement internal probe

1

0

 

BC0

An. Bndry. w/ series switch decoding

3

2

A,D

BC1

An. Bndry w/ small series switch, resistors

3

2

A,D

BC2

An. Bndry w/ 3 bits, gate decode

3

2

A,D

BC3

An. Bndry w/ 4 bits, gate decode

4

2

A,D

BC4

An. Bndry w/ 3 bits, switch decode, Update

3

2

A,D

A.B

Bias internal probe

2

0

A,D

A.I

Differential inputs to amplifier

4

2

A,D

A.O

Differential outputs from amplifier

4

2

A,D

Notes: A == Additional Analog Comparator with Early Capture

D == Digitizing Resolver.

3.0 The Boundary Cells

The IEEE P1149.4 test chip has a number of boundary cells, testing different options for switching AT1-4, VH, and VL to the various pins. In order to maximize flexibility, the VH, VL, and Compare lines are brought out to pins rather than to supplies and AT1; this allows tests simulating systems with multiple power supplies. Since we have differential inputs and outputs on the amplifier, we add an additional pair of stimulate and measure lines; the boundary cells connecting to these lines are slightly more complicated.

There are 11 types of boundary cells on the chip: DBIN, DBOUT, AB2, PROBE1, PROBE2, BC0, BC1, BC2, BC3, BC4, and BND2. The standard will use fewer cells; the variations allow us to test options. DBIN and DBOUT are 1149.1 digital boundary cells. AB2 connects the internal ATxBUS lines to the ATx pads. PROBE1 and PROBE2 are for internal point probing. BC0-BC4 are variations on the single pin boundary cell, while BND2 is a differential boundary cell for the differential amplifier.

The cells are shown in the attached schematics. Most of the cells use the "standard" three register truth tables:

Standard Three Register Truth Table

Switch

Connects

Decoded From

S1

Pin to Core

CD

S2

Pin to Vmin

PMODE Q1B Q2

S3

Pin to Vmax

PMODE Q1 Q2

S4

Pin to AT1BUS

AMODE Q1 Q2B

S5

Pin to AT2BUS

AMODE Q3

Capture for 3 Register Cell

Cell

reads back:

C1

XOR of Update latches U1, U2, U3

C2

Early Capture Comparator

C3

Digitizing Receiver

There is also a table describing the BC3 four register cell, and a table describing the BND2 cell.

Many cells have both a digitizing receiver and an analog comparator with early capture connected to each pin. Even if early capture or the analog comparator is broken, the cell will still be usable.

All boundary cells have clock buffers on the inputs, both to reduce skew on clocks as well as to minimize loading on the lines. This allows us to use simpler, transfer-gate style flipflops.

3.1 The Digital Cells - DBIN and DBOUT

The DBIN and DBOUT boundary cells are enhanced boundary scan cells, which capture inputs and multiplex outputs from the update latch. The DBOUT boundary cell has an extra scan flipflop; it captures not only the state from inside the chip (which in this case is the output of the DBIN cell) but also the state of the pin. Both cells have Early Capture latches, allowing measurement of propagation delay.

DBIN truth table

Function

Decoded From

IN

! MODE

0

MODE ! Q1

1

MODE Q1

The DBIN cell captures the output of the Early Capture latch; when the chip is not in early capture mode, the latch is in passthrough mode and the input comes from the pin.

DBIN Capture source

Capture Input

Decoded From

C1

Early Capture of Pin

The DBOUT cell is a two register cell acting like a unidirectional tristate buffer for test purposes - and as a unidirectional output buffer normally. The intent is to allow us to look at tristate on-off behavior as well as prop delay.

DBOUT truth table

Function

Decoded From

Passthrough Out

! MODE

High Z

MODE !Q2

0

MODE !Q1 Q2

1

MODE Q1 Q2

The capture is similar to that of the input cell. We capture in two different places to allow us to measure propagation delay:

DBOUT Capture source

Capture Input

Decoded From

C1

Early Capture from input to cell

C2

Early Capture from pin

3.2 The ATx Interface Cell - AB2

The AB2 cell is used to connect the internal AT1BUS, AT2BUS, AT3BUS and AT4BUS lines to their associated pins. The AB2 measurement output cell has a full complement of switches, and uses the SWS series decode switch structure that is used in most of the other "standard" boundary cells. There is no "core" connected to the cell. This cell is used four times. The cell has 3 update cells, and decodes from the following table (similar to other 3 register cells):

AB2 cell switch decoding

Switch

Connects

Decoded From

S2

Pin to Vmin

PMODE Q1B Q2

S3

Pin to Vmax

PMODE Q1 Q2

S4

Pin to AT1BUS

(or AT3BUS)

AMODE Q1 Q2B

S5

Pin to AT2BUS

(or AT4BUS)

AMODE Q3

The AB2 cell also has two capture cells; the C2 cell at the TDO end of the cell captures the pad end of the cell with a digitizing receiver. In addition, the C1 cell captures the same point with a CL analog comparator with early capture.

AB2 Capture source

Capture Input

Decoded From

C1

XOR of Q1, Q2, and Q3

C2

Early Capture from pin

C3

Digitizing receiver from pin

3.3 The Internal Probe Cells - PROBE1 and PROBE2

The PROBE1 and PROBE2 cells are used for internal connections. The PROBE1 cell has one control bit, which controls switches to both AT1BUS and AT2BUS, and captures its own update latch:

PROBE1 cell switch decoding

Switch

Connects

Decoded From

S1, S2

Core to AT1BUS and AT2BUS

Q1

PROBE1 Capture source

Capture Input

Decoded From

C1

Update Latch

The PROBE2 cell has separate control bits for the ABUS1 and ABUS2 switches:

PROBE2 cell switch decoding

Switch

Connects

Decoded From

S1

Core to AT1BUS

Q1

S2

Core to AT2BUS

Q2

PROBE2 Capture source

Capture Input

Decoded From

C1

Early Capture from pin

C2

Digitizing Receiver from pin

PROBE2 also has digitizing inputs from CORE; a digitizing receiver drives C2 at the TDO end of the cell, while an analog comparator with early capture drives C1.

3.4 The Analog Cells - BC0, BC1, BC2, BC3, and BC4

There are 5 test boundary cells, with the following variations:

BC0 Medium size switches, series decoded from 3 bits

BC1 Small size switches with resistors, series decoded from 3 bits

BC2 Medium size switches, gate decoded from 3 bits

BC3 Medium size switches, gate decoded from 4 bits

BC4 Small switches with resistors, series decoded from 3 bits, with UpdateDR gated by AMODE

Each switch has two pads, one connected to the normal PAD side and one connected to the normal CORE side. Since the CORE side pad is ESD sensitive, both sides of the core disconnect switch must be static protected. All core disconnect switches are made from 100 wide, 2 long N and P channel transistors; this large switch is necessary to provide sufficient junction area for ESD protection.

The BC0, BC1, and BC2 cells all have the same "standard" truth table:

BC0, BC1, BC2 truth table

Switch

Connects

Decoded From

S1

Pin to Core

CD

S2

Pin to Vmin

PMODE Q1B Q2

S3

Pin to Vmax

PMODE Q1 Q2

S4

Pin to AT1BUS

AMODE Q1 Q2B

S5

Pin to AT2BUS

AMODE Q3

Most of the switches on the test chip resemble the BC0 test cell.

BC0, BC1, BC2 Capture source

Capture Input

Decoded From

C1

XOR of Q1, Q2, and Q3

C2

Early Capture from pin

C3

Digitizing receiver from pin

The BC3 cell has a simpler truth table, with four control bits:

BC3 truth table

Switch

Connects

Decoded From

S1

Pin to Core

CD

S2

Pin to Vmin

PMODE Q2

S3

Pin to Vmax

PMODE Q3

S4

Pin to AT1BUS

AMODE Q1

S5

Pin to AT2BUS

AMODE Q4

BC3 Capture source

Capture Input

Decoded From

C1

XOR of Q1 and Q2

C2

XOR of Q3 and Q4

C3

Early Capture from pin

C4

Digitizing receiver from pin

BC0 and BC1 use "series" switching. Series combinations of switches are activated directly by the register outputs. The switches on BC0 are large enough to handle ESD currents, while the switches on BC1 are small and must be isolated by series resistors. The BC2 cell uses simpler switches driven by logic gates. The BC3 cell also uses logic gates.

THE BC4 Cell does not function normally; it is described below.

The BC4 cell is similar to the "standard" truth table of BC0, BC1, and BC2. Instead of gating the output cells with AMODE or PMODE, we instead AND the UpdateBND signal to the Update latches with ( AMODE | PMODE ). This was requested at the design review meeting, and allows the boundary register to move but prevents updates unless the AMODE and PMODE bits are enabled. This may not work, but allows us to try alternative behavior for the chip.

BC4 truth table

Switch

Connects

Decoded From

S1

Pin to Core

CD

S2

Pin to Vmin

Q1B Q2

S3

Pin to Vmax

Q1 Q2

S4

Pin to AT1BUS

Q1 Q2B

S5

Pin to AT2BUS

Q3

BC4 Capture source

Capture Input

Decoded From

C1

XOR of Q1, Q2, and Q3

C2

Early Capture from pin

C3

Digitizing receiver from pin

3.5 The Differential Analog Boundary Cell BND2

The BND2 cell is complicated because it drives two sets of PAD and CORE lines at once. The cell uses series transistors to construct the switches, like the BC0 cell and others. This cell uses 4 register cells to decode the various switch controls:

BND2 truth table

Switch

Connects

Decoded From

S1H

Pinh to Coreh

CD

S2H

Pinh to Vmin

PMODE Q2 Q3

S3H

Pinh to Vmax

PMODE Q2B Q3

S4H

Pinh to AT1BUS

AMODE Q2 Q3B

S5H

Pinh to AT2BUS

AMODE Q4

S1L

Pinl to Corel

CD

S2L

Pinl to Vmin

PMODE Q1 Q3

S3L

Pinl to Vmax

PMODE Q1B Q3

S4L

Pinl to AT3BUS

AMODE Q1 Q3B

S5L

Pinl to AT4BUS

AMODE Q4

(table revised 5-19-96)

The four capture inputs are used to capture digitizing receiver and early capture analog comparator versions of the PADH and PADL lines, like so:

BND2 Capture source

Capture Input

Decoded From

C1

Early Capture from Pad L

C2

Early Capture from Pad H

C3

Digitizing receiver from Pad L

C4

Digitizing receiver from Pad H

4.1 Differential Amplifier

There are two nearly identical differential amplifiers on the chip. The first amplifier is connected straight to the pads, with no test circuit encumbrances besides being turned off by CD. The other amplifier has series switches for core disconnect at the input and output, and full boundary cells connected to it.

The amplifier is a simple differential amplifier, working against ground. The input common mode range is 0 to 2 volts, and the output common mode is about a volt. A voltage gain of 5 into a 50 ohm load is expected. The circuit consumes about 80 mA, but may be disabled from the status register, or by CD. The circuit uses P channel devices, in order to limit the bandwidth to around 100MHz. The amplifier has no special correction for linearity, so there will be a detectable 3rd order distortion for large signal swings.

While it would have been possible to construct a much better amplifier, a more complicated amplifier would be more risky to build and harder to measure. If the amplifier is too good, its defects will take too much work to find.

4.2 Pin Comparator

The pin comparator has raised a lot of stink about size and power, which is unfortunate; a very fast comparator can be constructed to resemble an SRAM sense amplifier, strobed by the Early Capture pulse. Such a comparator uses zero static power, and can compare voltages with millivolt accuracy anywhere between the supply rails.

While it is possible to incorporate the comparator inside the master portion of a boundary scan flipflop, risk can be minimized by making the comparator a separate latch on the path into the capture input of a normal scan flipflop. The capture latch is shown in the schematic "CL".

4.3 ATMS

This circuit resembles an idea by Dr. Dandapani of Colorado State, which combines the TMS pin with the ABUS1 pin. Rather than risk the design by modifying either the TMS pin or the ABUS1 pin, an additional pin is used, which can be connected externally to ATMS by Dr. Dandapani to test the idea.

The ATMS proposal, as implemented here, utilizes the fact that TMS is ignored when it is not being sampled on the rising edge of TCK, and that it is distributed to all the chips that use ABUS1. During the first part of the Run-Test-Idle state, a rising edge on TMS causes a device equipped and programmed to enter the ATMS state to connect the internal ABUS1 line to the TMS pad (or in this case the ATMS pad), while the test controller drives analog stimulus into TMS (or ATMS). TCK is held high while the measurement is made; at the end of the measurement TCK drops to zero and the chip and controller return to normal digital function.

Note that the ATMS period is separated from both the TMS sampling points. If there is an analog short to ground or supply on a pin connected to ABUS1, we do not want to interfere with the transmission of the digital signal to other devices connected to TMS.

The ATMS feature, as implemented, should not interfere with the rest of the chip. If for some reason the switch is stuck closed, the ATMS pad doesn't connect to anything else.

The Early Capture idea presented below also makes use of the underuse of TMS, extracting an extra edge on TMS during the Update-DR state.

5.1 Early Capture

The standard 1149.1 implementation does not make measurements of propagation delay easy. Normally, data on output pins changes on the falling edge of TCK during the UpdateDR state. The data is captured on the rising edge of TCK during the CaptureDR state, which is at least 2.5 clock cycles later. Since the clock rate of TCK is constrained to the clock rate of the slowest chip in the scan chain, while propagation delays of interest may be a fraction of one clock cycle, we are unable to tell whether the circuit under test is propagating signals rapidly enough.

The early capture extension to the standard proposed here is a method to measure propagation delays that are fractions of a clock cycle. Devices with the extension can be programmed to sample input data immediately after the assertion of UpdateDR, while other devices without the extension operate normally. This extension makes use of the fact that TMS is a logic 1 entering the UpdateDR state, and is only observed on the rising edge of TCK. Thus, extra or skewed transitions on TMS are ignored by the TAP logic.

Since TCK and TMS usually have equivalent loads, the propagation delays and skews on the falling edge of TCK can be made to match those on a falling edge of TMS. If the falling edges are launched by the tester at the same time, they should arrive at any given device at the same time, and should be subject to the same switching artifacts. Thus, with precision control of the relative timing of the two edges at the tester, we should be able to accurately control the relative times these two pulses arrive at the device.

Since we are free to vary TMS when the TAP logic isn't sampling it, we can always inject a falling edge on TMS at any time after the rising edge of TCK that samples TMS and moves the tap into UpdateDR state. We can control the relative placement of these edges with great accuracy. Early capture uses a properly placed falling edge on TMS to store pin data into an extra latch added in front of the normal capture input. As a result, input data may be captured just before or after UpdateDR is asserted.

A typical boundary cell, modified for early capture, is shown:

Early capture is programmable on the extended chips, either as a special set of instructions or as a control bit in an auxiliary data register. Thus, it can be turned off, and chips with the extended capture capability can be made to appear like a standard chip.

Extending TAP and instruction decoding for early capture are fairly simple. A simple RS latch is set high by a combination of the UpdateDR state being asserted and TMS going low, and set low by ShiftDR. The result is NANDed together with the appropriate instruction bit or control bit enabling the early capture condition. Whenever early capture is implemented on a chip, provisions should always be made to not use it to insure full compliance with the standard.

The additional cost of early capture to a typical chip is an additional line running around the chip, plus one additional latch for each capture input with the extension. A boundary scan chain can have a mixture of extended and standard non-extended cells, and the extension can be added to either digital or analog boundary cells.

Typical waveforms for a chip with early capture mode are shown:

Dashed lines show the normal, standard times of edges without early capture.

When early capture is enabled, the new signal early capture is allowed to pulse low. All the standard JTAG signals stay the same. The early capture pulse goes low when TMS goes low during the UpdateDR state and goes high when ShiftDR is asserted, causing data to be held from the falling edge of TMS until after it is captured by the normal CaptureDR pulse. The falling edge of TMS occurs naturally if we are transiting to the Run-Test-Idle state (shown last), but has to be inserted with an artificial negatively going pulse if we are leaving TMS one and transiting directly to the SelectDR state (shown first).

In some systems, we may want to measure a propagation delay that is longer than the half-clock cycle shown here. In such systems, one may simply mask out a few of the positive TCK pulses, and thus "hold" the system in the UpdateDR state until it is appropriate to drop TMS and perform the sample. Thus, very long propagation delays may be measured.

5.2 Measuring Waveforms with Early Capture

Given a synchronous repetitive waveform, an analog comparator, a programmable voltage level, and a programmable delay between two edges, a waveform can be extracted and displayed after a few hundred or thousand binary tests. If only specific test measurement questions need to be asked, such as whether risetime to 90% is less than a certain amount, the above setup can generate answers with just a few measurements. Some measurements, such as measuring peak-to-peak signal levels on asynchronous waveforms, are statistical in nature and can take a lot of measurements to get accurate results; nonetheless, they can be done if the test setup is cheap enough to dedicate to the measurement for a while. Certainly the low cost of a JTAG test - in many cases no more than special code built in to the system processor - makes this possible.

We will illustrate two cases: waveform extraction, and asynchronous IF carrier level measurement. For the waveform, approximately N*B comparisons are needed, to extract a waveform of N points to B significant bits. For the carrier level, about 2(2B+3) comparisons will yield B significant bits of carrier level - assuming the comparison is truly asynchronous to the carrier being measured.

The waveform measurement is simple: for a set of increasing time points, perform a successive approximation of the voltage at each time point. We set the time point by setting the time difference between the TCK and TMS edge. Assuming the comparison voltage is being delivered by AT1, we do a binary search, adjusting the AT1 voltage from a DAC in the test controller. B comparisons are necessary for B bits. More comparisons may be required if the waveform is noisy.

Carrier extraction is harder, but still possible. We rely on the fact that the probability that the comparator output is logic one when randomly sampling a sine wave follows the following arcsin() function of the comparator voltage level:

We can take a few samples, and look for the voltages at which p(VL) @ 0.25 and p(VH) @ 0.75. (These probabilities don't need to be exact). We then take 2(2B+2) samples at each voltage, to get a more exact value of p(VL) and p(VH). With those values, we can compute the peak-to-peak carrier value with the following formula:

VP-P = 2 ( VH - VL ) / ( cos( p p(VH)) - cos( p p(VL)) )

If there is random noise on the signal, the process is a bit more complicated; the above probability function is convolved with a Gaussian whose width is proportional to the peak to peak noise. The function changes shape, but the computation of carrier peak to peak level will be similar.

If we want to learn even more about our carrier, we could measure the probability curve at a number of sample points, and estimate waveform distortion. However, our comparator itself may distort the signal, so this approach only works with very good comparators and very bad carriers.

Of course, if we can synchronize the sample time to the carrier, we need only take 2B samples to measure carrier level. This can be done by running the carrier through a limiter, measuring the period, and delaying the appropriate times to measure the levels of the peaks. With this type of setup, we can measure AM and FM modulations. How? This is an exercise left for the reader...

6.1 Implementation

The JTAG analog test chip is expected to be a 40 pin rectangle somewhere in a larger IMP 1205 process (1.2 double layer metal CMOS) test chip. The test chip will have it's own scribe lane, and will be separated from other proprietary IMP chips. With 10 pads per side, and 200 micron pad spacing, the test chip will have an active center about 1900 x 3400 microns. About 30% of the chip will be occupied by the TAP controller and instruction register, another 30% occupied by the capture/update cells and switches, and 20% occupied by the differential amplifier. There will be plenty of room for other experiments - implementation time will be the main issue in determining what goes on and what is left off.

The KLIC TAP has been used on a number of circuits on different processes for varied customers. On a 1.2 process, it will run at about 20MHz worst case; it has been optimized for speed rather than size. It may, however, have flaws in it's JTAG implementation that my customers haven't noticed. It will need scrutiny.

The cells used on this circuit are proprietary. KLIC can't stop anyone from reverse engineering them, but please don't break my rice bowl - if you need cells, KLIC can design them for you cheaper than you can reverse engineer them.

KLIC does simulation with HSPICE and PSPICE on a Pentium; logic simulation is performed with SILOS2. Schematics with ORCAD, layout with Tanner LEDIT, and extraction with Berkeley MAGIC. Pattern output is either CIF or GDS. A final check with Cadence Dracula will occur at IMP. KLIC is on the Internet and can reach the Dracula site via dialup or FTP. This kludgey setup has produced half a dozen chips that worked the first time, including one with 700K transistors.