February 8-9, 1996
|11:45am||Lunch - Thank you Seagate|
|12:00pm||Arrival and Introductions||Adam Cron|
|12:15pm||Approval of October, 1995 Minutes||Adam Cron|
|12:20pm||4-wire Analog Bus||Robert Russell|
|12:30pm||.1/.4 Integration||Adam Cron|
|2:00pm||Break - Thank you Seagate|
|2:30pm||1149.1/P1149.4 Integration - Continued|
|3:00pm||Definition of Switch||Ken Parker|
|4:00pm||Differential Cells||Steve Sunter|
|5:00pm||Should Inputs Drive||Ken Parker|
|5:40am||ITC Papers||Gordon Robinson|
|5:45am||Next Meeting in May, 1996||Adam Cron|
|6:00pm||Adjourn for Day||Adam Cron|
|8:00am||Arrival and Introductions||Adam Cron|
|8:05am||Differential Cell Proposal||Steve Sunter|
|8:15am||Draft D05 Progress Report||Adam Cron|
|9:00am||Patent Issues||Mani Soma|
|9:30am||IC Test||Mani Soma|
|9:45am||Balloting Schedule||Adam Cron|
|10:00am||Break - Thank you Seagate|
|10:30am||IC Progress Report||Steve Dollens|
|11:00am||1149.4 Compliance||Steve Sunter|
|11:30am||Digital vs. Analog||Steve Sunter|
|Working Group Members||34|
|Total Subscribers on "esd" reflector||240|
|William Allen||Seagate International|
|Dan Dandapani||University of Colorado|
|Steve Dollens||International Microelectronic Products|
|Miles Ito||Panasonic Semiconductor|
|Terry Junge||Seagate International|
|Adam Ley||Texas Instruments|
|Elbert Nhan||Johns Hopkins University|
|Gordon Robinson||Credence Systems Coporation|
|Mani Soma||University of Washington|
|Lee Whetsel||Texas Instruments|
|Madhuri Jarwala||AT&T Bell Laboratories|
|Brian Wilkins||Southampton University|
Ken Parker introduced the WG two new attendees: Mr. Miles Ito of Panasonic
and Mr. Koji Oka of Matsushita. Adam Cron stated that the current WG membership
policy is such that interested individuals may become a Working Group member
by attending two of three meetings. Mani Soma added that NEC also is reportedly
interested in joining the WG.
Adam talked about the IEEE patent policy. In a letter from the Chairman
of the IEEE Standards Board, Donald Loughry, to the Honorable Donald S.
Clark of the Federal Trade Commission, Mr. Loughry urged the FTC to clarify
the intent of its decision on the Dell patent matter. The main point of
the letter is to request the FTC to avoid imposing restrictions and regulations
that could jeopardize the current standards-setting process. The IEEE's
position is that implementation of standards may include known use of certain
patent(s) if there is technical justification and provided an assurance
could be obtained, without coercion, from the patent holder(s) who will
agree to license applicants under reasonable terms and conditions to practice
the standards. The assurance shall be in the form of a) a general disclaimer
and b) a statement that a license shall be available to all applicants
without compensation or under reasonable rates. The IEEE does encourage
EARLY disclosure to a working group of any relevant patent information
through the working group chair requesting known patent holders to submit
a statement stating either the patent does not apply or if it does, licenses
shall be made available either without compensation or under reasonable
terms and conditions. Again, the key words are "NO forcing anyone
to disclose patent information."
Adam asked if anyone has any problem accessing the ITC minutes. Lee
Whetsel said he was still experiencing problems. Adam announced the minutes
are on the web and anyone can access it who has access to the WWW. The
URL is "http://grouper.ieee.org/groups/1149/4/min1095.htm".
Adam motioned to approve the ITC
(10/95) meeting minutes. Seconded. Unaminous approval.
At the ITC meeting last October, Steve Sunter raised the issue of adding
pins to an IC beyond those required for 1149.1, translating to an increase
in costs. Bob is proposing a 1149.1 test method that will allow mixed-signal
testing with the existing 4 1149.1 wires instead of 6. Basically, this
is a scheme that employs a modified 1149.1 interface that combines concepts
of 1149.1 and P1149.4 operating on a 4-wire bus. Depending on the type
of test, one may switch between analog and digital measurement circuitries
as shown in the diagram which illustrates a stand-alone
test system controlling a string of ICs to the left and the sequence of
operations necessary for this scheme. Gordon pointed out this system cannot
co-exist with a 1149.1 scan path if any of the analog test methods were
invoked. For viewgraph 2, Lee pointed out there
is a patent that governs the direct path (bypass) from TDI to TDO. Instructions
on how to use this scheme were shown in viewgraph
3. This proposal is based on Bob's patent with a similar scheme whose
technical contents are shown on Mani's viewgraphs.
An IC with digital 1149.1 with mixed-signal compatibility on a 4-wire bus
is shown in viewgraph 4. Viewgraph
5 shows how to use TRST to save some test circuitry. The key is to
be able to get down to a 4-wire configuration. Ken commented that people
will accept simple solutions (1149.1 has been accepted), bed-of-nails,
100 % access, etc., but they still don't know what to do with the analog.
There is a tendency to resist adding more and more pins, and this 4-wire
configuration is certainly an option, or use Dan Dandapani's proposal.
Mani pointed out that 1149.1 still has not approved any of these proposals
yet, and Adam will motion to this WG to vote on Dan's and Bob's proposals.
Dan said that we should have a 1149.1 that will be compatible with future
1149.1 chips but Steve Sunter said we need a standard that will be backward-compatible.
We don't want something that would make existing products obsolete. Dan
added that we could have a disconnect on the board. Meanwhile, Mr. William
Allen of Seagate joined the meeting in progress.
Adam said at yesterday's 1149.1 meeting, discussion of issues between
1149.1 and P1149.4 was held by going through the 1149.1 document page-by-page.
The 1149.1 WG has already motioned in Lee's proposal on 1149.1 pins. But
a sticky point remained: they optioned in (see viewgraph)
the blue and green cells with the third configuration on the viewgraph
being the most ideal. The one at the top is the existing 1149.1; the example
in the middle is more of a compromise (no INTEST is possible). Gordon said
INTEST is still "very fragile" in 1149.1. With the changes made,
it is now left to the 1149.1 editor, Adam Ley, to word it in the document.
Steve Sunter said P1149.4 has no control over the inputs and that if no
INTEST is needed, the middle example (on the viewgraph) is sufficient.
Adam Cron said that is up to 1149.1 to define. Adam Ley said that's a subtlety
that has not been addressed. At the moment, the one at the top of the viewgraph
IS mandated. Ken suggested P1149.4 members should probably be in the 1149.1
WG as well. The blue & green cells are now OPTIONAL, not mandatory.
We now have three options. Other changes (in chapter 10) discussed yesterday
will be made to accommodate Lee's EXTEST proposal.
SUMMARY: Two major changes were made in 1149.1 at the most recent
1. It was agreed to append at the end of chapter 3 of 1149.1 a section
that specifically allows for the extension of the TAP which currently has
4 pins. This is to ensure the rest of 1149.1 is still compatible without
the 2-pin extension to avoid wholesale changes to 1149.1. In other words,
if the two pins were taken out, 1149.1 should continue to apply; that is,
the addition of those 2 pins must not disturb 1149.1.
2. The 1149.1 WG agreed on the principle in the viewgraph that contains
the three options. But the details and specifics will be worked out by
both 1149.1 and P1149.4 WG members (1149.1 Editor Adam Ley leads the task).
The Working Group decided, after deliberations, to form a small subgroup
to outline 1149.1/P1149.4 issues that would be presented to 1149.1 at the
1149.1 Working Group meeting on Thursday. The idea is to make recommendations
to 1149.1 based on Lee's proposal to have changes in the 1149.1 Standard
made so that P1149.4 would be compatible with 1149.1.
Refer to Brian's E-mail dated 1/26/96 (also on handouts and viewgraphs)
for the following discussion.
Brian concluded that chapter 3 of 1149.1 needs no changes. Adam, in Brian's
absence, proposed the following motions on Brian's behalf:
MOTION: Do not accept Dan Dandapani's 5-pin, ATMS proposal as a
solution for this P1149.4 Working Group to propose for a Draft ballot.
Seconded. Yea: 10. Nay: 0. Abstention: 0. Unaminous approval. Motion carried.
MOTION: Do not accept Bob Russell's 4-pin, multiplexed pin arrangement
as a solution for this P1149.4 Working Group to propose for a Draft ballot.
Seconded. Yea: 10. Nay: 0. Abstention: 0. Unaminous approval. Motion carried.
A motion was proposed based on Brian's E-mail as follows:
"To claim compliance to 1149.4, ALL pins must be addressed with the
resources of this standard. This motion would supersede a motion passed
on 10/22/93 which stated that at least TWO pins needed to be addressed
by the standard."
Steve Sunter asked if it is per-pin or per-chip. Should we allow for
a purely digital chip to have P1149.4 compliance? Discussion ensued. Steve
said that earlier we have basically decided on the definition of what P1149.4
1. 2 ABUS pins and an ETAP.
2. Analog pin without parametric test should be documented, acknowledging 1149.1, chapter 12.
3. Digital pins on P1149.4 chip shall conform to 1149.1 and may have parametric capabilities.
Adam Ley said we should really say a P1149.4 compliant chip shall have
1149.1 and the above. Also, analog pins must have EXTEST. Gordon suggested
we should obtain and collect all the wishes and desires that people have
and work on the wording based on those. Gordon believed that the middle
position is the only one that will work. Practical considerations and issues
need to be addressed, and exceptions acknowledging them should be allowed.
The sentiment is that we should require people to conform to the requirements
but do give exceptions for practical concerns. In other words, a chip that
is P1149.4 compliant will have 2 ABUSes, and 1149.1 capability on all pins
(which has already been motioned in).
Lee presented his viewgraph which shows three
different cases: 1) A P1149.4 chip (with analog pins and ETAP). 2) A P1149.4
chip even though only one pin is P1149.4 (with an ETAP). 3) A P1149.4 chip
if 6 pins are required for core logic interrogation; if analog function
is completely confined within the chip but not present at pins, then to
test the internal analog function we would need a 6-pin TAP -- that would
still make it P1149.4 compliant. Question arose as to if we have an analog
pin, does that pin necessarily have parametric capability? Maybe. We should
have some example pictures like those on this viewgraph
in the document.
Gordon came up with a viewgraph in an effort
to address the 1149.1/P1149.4 compliance issue. Each column represents
an example chip category. Could the "wet cell" (referring to
the cell design proposed by Lee Whetsel) and P1149.4 measurement co-exist?
Lee said if there is a TAP, then every digital pin will have a cell. Adam
Ley said maybe we should focus on the function (EXTEST, INTEST, etc). Steve
pointed out that before any coherent discussion can take place, we must
clearly define the terms:
1. ".1" -- simple interconnect.
2. "wet cell" -- analog pins with digital capability (without core disconnect for 2-state and with core disconnect for 3-state).
3. ".4 meas" -- parametric measurement excluding 1149.1 simple interconnect (includes capability to drive high and low).
Mehdi Katoozi asked why distinguish between digital and analog pins;
why not just call it a pin? Steve tended to agree saying perhaps we should
not classify pins as digital or analog. Adam Cron said we have motioned
in G and core disconnect, but not +V. Ken chimed in saying maybe we should
add core disconnect to P1149.4 which would make it halfway to 1149.1. What
about power pins? 1149.1 specifically mentioned there shall be no cell
on power pins since signal and power pins/distribution are two separate
things. Also, +V and G and pure power pins are different. Mani asked if
an action item needs to be initiated for this topic. Adam said we could
debate over the e-mail, and the issue was tabled.
ACTION ITEM: Steve Sunter is to produce definitions for the terms
on Gordon's viewgraph. Adam asked if there were
any additional definitions other than those shown on the viewgraph.
Gordon said both WGs need to jointly work on this viewgraph.
The discussion of this topic is deferred until we have Steve's definitions.
SUMMARY: Two motions were passed. The issue of 1149.1/P1149.4
compliance spurred intense discussion and debate on per-pin/per-chip issue.
The lack of clear definitions for "1149.1 compliance" and "1149.4
compliance" appeared to hinder progress.
There has been some discussion on what the definition of a switch is.
We need it so Brian Wilkins can insert it into the P1149.4 document. Steve
Sunter, Ken Parker, and John McDermid have discussed at length about this.
Mani pointed out we probably should use a black-box model. Presently, there
is no answer on what that model is yet. A subgroup that is devoted to this
issue should get together and work it out face-to-face. Ken suggested himself,
Steve, Mani, Keith, Dan, and John McDermid. Mani commented that it is not
as simple as it sounds to define a switch. Mani pointed out a switch that
only switches from high to low is simple but switches that have core disconnect,
bidirectionality, etc., are rather tough to design. Steve said nothing
in P1149.4 mandates bidirectionality. What about a G switch which needs
to be able to source and sink? Steve said the only requirement for G is
it has to be stable. This comment was followed by debate on how to measure
a capacitor and whether we need bidirectionality in this situation. The
need to discharge a capacitor will have bidirectional and sink-source requirements.
Ken re-iterated the need to get together face-to-face. Lee asked what to
do about inductors. Steve said everything said so far about a capacitor
should be considered for an inductor. There was a suggestion to use DC
instead of AC to measure a capacitor.
ACTION ITEM: Ken Parker to lead a subgroup to study the switch
issue. The members include John McDermid, Mehdi Katoozi, Steve Sunter,
Keith Lofstrom, Mani Soma, and Dan Dandapani.
Refer to Steve's viewgraph (shown below) entitled "Handling Differential
Pins." How do we accommodate differential pins? With the current ABM
(analog boundary module). He is proposing differential cells that have
opposite voltages, but Keith said there are exceptions to that. The proposal
is for each pin to have an ABM, and be treated the same as singled-ended
pins. Differential capability is necessary for noisy environments. 1149.1
mandates the second bullet on the viewgraph. Differential pins are considered
analog in 1149.1. We need a single-ended bit on each pin. 1149.1 also mandates
one cell to capture the output of a differential pin. Ken said maybe board
test engineers are not interested in differential results but Steve disagreed.
Debates continued on the second bullet on the viewgraph (people are
buying bullets 1 and 3). There were sentiments for a motion to be on the
floor. More discussion followed. Adam Cron drew on the viewgraph to illustrate/explain
the difference between a single reference used for differentiating between
a high and low input, and a differentially generated high and low (they
reference each other). Input pins get differential resolution capability
for free but we need a comparator on the output pins. The gist here is
whether we need a 7th bit to capture the output or use one of the 6 bits.
In one of the viewgraphs, the green rectangles
are full ABMs. [This viewgraph is illustration for the next day's discussion.
The original, similar viewgraph is lost.] The comparator, Steve suggested,
be green, too, showing that it belonged attached to the ABMs. Lee Whetsel
said that as soon as CD is enabled, it will put the green rectangles into
EXTEST because the control is a global signal, and would block the output
of the differential driver. This can be seen better in this viewgraph.
The result is we would be capturing what is on the pins, and not what the
differential driver is outputting. EXTEST does not work for differential
cells. A new instruction would solve this problem quick and simple. John
Andrews probably had this new instruction in mind. Steve said there is
no need for a new instruction and will come back with a revised proposal
tomorrow. Ken said if we must have a differential structure, we would be
trying to solve both manufacturing test and field test at the same time.
Maybe either but not both. The point Steve was trying to make is: to accommodate
Keith Lofstrom, we should be able to disable one or both the + and - pins.
This is EXTEST. The only combination we should forbid is the ability to
drive both high or low. But Ken said we need both high and low for interconnect
test. Adam asked if we can have a new instruction? Ken's reply was that
would also affect 1149.1 but 1149.1 does not need it. Adam said that would
apply to the general case, not just for differential. The final consensus
was to look into the issue of the general case. The topic will be re-visited.
SUMMARY: Steve Sunter proposed a scheme that handles differential
pins without resorting to creating a new instruction.
This is proposing a digital paradigm in a non-digital world. A lot of
cases do not have just simple wires. In his viewgraph,
input is on right and output is on left. In Ken's example of capacitors,
point A is not necessarily equivalent logically to point C; so we cannot
find shorts or opens. In this instance, treat each of the 4 points as independent.
Treat all the analog pins independently. Hence, there is a need for receivers
and drivers on all 4 pins in this example. Why did this question come up
in the first place? P1149.4 is an extension of 1149.1. Adam Ley said the
"wet cell" is implemented so we can add testability to analog
pins. The "wet cell" is an incremental addition/improvement to
1149.1. Adam seemed to question the real value of "wet cells"
since only P1149.4 interconnects have complex connections. Ken summarized
by saying that if inputs do not have drive capability, we would lose testability
for cases similar to what is shown in the viewgraph.
If one added a terminating 50-Ohm resistor at D, and B is a "strong"
driver, then we should be able to detect a fault. A question was raised
concerning what to do if someone wanted to measure the value of the capacitor(s)
which would not get picked up by this method. If there is a fault, then
if one attempted to measure the capacitor values and the fault happened
to be an open, we would get a spurious value. These are some of the issues
that 1149.1 has to address before Adam Ley can draft it up. Ken had a motion
on the floor: P1149.4 will treat all analog pins in a structurally uniform
manner independent of the system use of the pin. Discussion: Clarify the
implications of treating all pins the same and not distinguish inputs from
outputs like in P1149.4. Mehdi prompted Ken to amend the motion by adding
"with respect to the resources required for interconnect testing."
Therefore, the final version of the motion is as follows:
MOTION: P1149.4 will treat all pins in a structurally uniform
manner independent of the system use of the pin, with respect to the resources
required for interconnect testing. Seconded. Yea: 12. Nay: 0. Abstention:
0. Unaminous approval. Motion carried.
Gordon announced the deadline for ITC papers and panel discussion topics
are being solicited. Gordon suggested a panel session for "experience
with the test chips." Ken said we could probably add to this ad-hoc
tests that can be done to attract audience. Mehdi suggested getting designers
to take positions on issues. Gordon said he is entertaining suggestions.
Lee cautioned there may be tough questions.
Gordon said before sending ballots out, distribute the draft to WG members
to review, word-by-word. Gordon warned we would get a lot of comments.
By having a meeting to go through the draft paragraph-by-paragraph, we
will get it ready for ballot. We also need to get a balloting group formed.
Adam Cron would supply a list of group members to the IEEE which is fundamentally
in control of the balloting process. All of the 1149.n ballots done in
he past had been done with compiling a list of people that showed genuine
interest. Invitations for balloters go out with wording that warns being
a member of the group means a serious commitment of time. This is done
to discourage people from attempting to get a copy of a standard for free
by merely verbally agreeing to be a balloting member. Adam Cron needs to
draft a letter for IEEE to send out and the IEEE will put a clock on the
ballot. The day on which 75% of the ballots come back is when the ballot
will close. The balloting fails if 75% is not reached. Even responses of
"not enough time" are counted as part of the 75%. In P1149.1
balloting, a few negative responses were received and dealt with. Consideration
of comments included with the responses may result in another draft version.
P1149.1 received a few hundred comments. Then re-balloting is done for
the revised draft. The vote remains the same if no responses are received.
Gordon suggested nominating a balloting subgroup to take care of this business.
A small subgroup of the WG should do the job, not the entire WG. At the
time the ballot goes out, it is necessary to coordinated with groups listed
on the PAR. At this point, Adam Cron will coordinate the mailing with Luigi.
Two possibilities: Quebec (2nd IEEE Mixed-Signal Testing Workshop) 5/15-18/96,
or Atlanta (International Symposium on Circuits and Systems (ISCAS) '96,
5/12-15/96. The issue of WG meetings with conference tie-in again was raised.
Could HP sponsor it? This came up because Canada travel is difficult for
most people. What about VLSI Test Symposium? It is more for the digital
community. HP in Loveland? Ken will be out in June. The site selection
for next meeting was tabled for e-mail discussion.
A straw vote was taken on the cities as a possible site for the next
P1149.4 WG meeting.
The WG adjourned for 2/8/96.
Meeting resumed the next day, 2/9/96:
Adam and Ken introduced a new attendee, Mr. Akira Matsuzama of Panasonic,
who is interested in attending and possibly joining the P1149.4 WG.
Steve Sunter's proposal for differential in the general case (action
item from 2/8/96):
Steve revised his viewgraph -- core disconnects
go inside the red differential amplifier. One may put a 1149.1 cell between
core and differential amplifier but it is logically redundant (at the "+"
and "-" pins, a "1" or "0" can be expected).
The key is to move the CD from the core to the differential amplifier.
This amounted to a minor change in Steve's "Handling Differential
Pins" viewgraph as follows:
Also, the third bullet on the same viewgraph
was taken out.
To summarize, this is still conceptual for an input, output, or I/O.
The ABMs at the pins will monitor each of the pins independently and the
comparator at the bottom will monitor the difference between the two pins.
In effect, what has changed from 1149.1 is: the cell between the core
and differential amplifier is not necessary if differential capability
is to be used. The problem with not having cells in the driver is that
it puts constraints on the test generation. Adam Ley said this is an issue
1149.1 needs to examine closely. Adam Cron asked, with regard to software
constraints, what can be done? Ken said it is probably doable.
A motion was proposed on the revised viewgraph.
There is already a comparator in each ABM. But the third comparator shown
in the viewgraph is optional. Lee questioned the need for the third comparator.
The comparator in each ABM is referenced to a local mid-rail; so we need
the third to resolve the differential signal. Steve said in a noisy environment,
it would give a different result. The issue was a need for a fixed reference.
As sketched on the "handling differential pins" viewgraph, logically
combining the outputs of two comparators is not the same as the output
of a comparator taking the difference between the two.
Terry Junge and Mehdi wanted the comparator optional. Ken also agreed
that it should be made optional, which is not uncommon in 1149.1 where
there are lots of options. The reason for making the comparator optional
is that the only function of the comparator is to provide a difference
of the two signals. Ken suggested this motion to be included in the draft
to show designers what to do and give examples in the document for differential
cases. This scheme is for both board and field tests. Both Ken and Adam
were in favor of documenting in the draft what we have found for differential
pins to provide guidance for designers to handle differential situations.
Lee wanted the input and output cases separated, but this scheme is for
input, output, and I/O. Ken said regardless of whether the pin is an input
or output, it should be stated in the Standard that one must obtain the
DIFFERENCE of the signals.
In summary, the purpose of this presentation is to clarify how to deal
with differential pins and at the same time be consistent with what we
have so far. We are still treating the pins like any other pins but the
addition of the comparator will turn them into differential pins. Perhaps
the differential pin information can be made an application note. Adam
Ley said there must be some special treatment for differential pins for
BSDL's sake. BSDL is designed to mirror the Standard. Therefore, if this
is the way to treat differential pins, then we need to put it in BSDL.
Ken re-iterated he still would like to see examples in the document. As
a result of the above discussion, the following motion was proposed.
MOTION: Handling differential pins -- 1) each pin shall have
an ABM, 2) optional: comparator across pin pair, with its output captured
by 1149.1 input sample, 3) include examples in Standard. Seconded. Yea:
10. Nay: 0. Abstention: 1. Motion carried.
Adam Cron reminded the WG that we need to review the draft in detail
and will ask Brian to draft version D06 as if the appropriate changes were
made in 1149.1 before the next meeting.
Mani Soma presented information regarding Bull HN Info Systems patent
authored by Robert J. Russell's (member of 1149.1 and subscriber of P1149.4)
#5,404,358 entitled "Boundary scan architecture analog extension",
filed on Feb. 4, 1993, and granted on April 4, 1995. He commented that
sometimes the site works great, other times, not so good. Bob Russell's
presentation yesterday was on a parallel scheme vs. the one in his patent
which is serial. How does the patent relate to P1149.4? Lawyers recommended
looking at the draft, the WG minutes for the past 2 years and the patent,
and determine if any infringement exists. Mani will consult with the IEEE.
The Dell and VESA patent issue: the essence of the whole matter is that
the standard setting process takes precedence over patents by individuals/companies.
Dell agreed to follow the rules but did not admit to any wrongdoings. However,
the FTC specifically listed the violations. More information is available
on the web site mentioned. This patent issue is the basis for the IEEE
Standards Board letter to the FTC discussed at the beginning of these minutes.
Mani also mentioned the P1149.4 logo and T-shirts. Check the web for
colors and pictures.
Final comments on patents: A standard-setting group should have companies sign waivers, not just verbally indicating no knowledge of any infringement. Besides, meeting minutes and materials are open to the public.
The purpose is to find any limitations, anything we have not thought
of before. We want to determine the accuracy of components vs. test time.
Mani pointed out the chip wasn't optimized at all for performance but instead
is intended for finding practical limitations. Steve's viewgraph (listed
below) shows guidelines for measurements to verify a number of key concepts.
Mani said the test chips are intended to be demo chips for the industry
to find out what P1149.4 can do for EXTEST, etc. He showed a test suit
for the demo board that includes power-up and initialization test and test
bus structure integrity tests (see slides, below). For EXTEST, check for
consistency with 1149.1 and P1149.4 standards with the different types
of tests. Termination of test mode may be a bit involved. Steve Sunter
stated that people should realize there are important differences between
two seemingly similar differential amplifiers (one with P1149.4 and one
without). Keith found mistakes on the logic of the controller which never
got checked out. Mani did examine the analog scan cells. He suggested the
group get together again and check the layout. He wanted to have chips
working before this year's ITC. We might be able to get a nice interface
software from two 1149.1 support companies under Windows for P1149.4. It
is necessary to get the group together and verify the design and have Steve
Dollens's commitment to fabrication (6 weeks?), but software will take
longer. It would be nice to have a menu in Windows for people to select
and use. Bill Coombe said with the problems Keith found, it will take longer
than originally expected to test the chips. Adam Cron said that metal layer
does not have to be fixed for the chip to work by manipulating software
to get around it.
Adam put Steve Sunter's viewgraph up and assigned names to the various
tasks listed. These tests should be completed by September 30, 1996.
Bill mentioned Medtronic got the test fixture and 80% of the test software
done before Keith found the problems with the test chips. Apparently, the
turnaround time for the test chip to be fixed is still in question. With
the repaired test chip and the interface software from Intellitech/ASSET-Intertech,
we could probably have working test chips by ITC.
SUMMARY: Test plan was laid out for the test chip fabbed by IMP.
Keith Lofstrom found some logic problems with the controller that were
not detected during layout check. One option is to fix the layout problems
and fab new chips which may take some time, and another option is to work
around the problems with software.
Four test chips have been fabbed (Rev. A). These chips were built into
an IMP test structure. Approximately 20 chips will be shipped from Singapore.
Adam Ley volunteered to do the interface for FIB rework. Need 20-30 FIB
for test devices. Keith will provide information on what to cut in the
masks. Keith and Steve Dollens will discuss the mask changes. IMP is about
3-4 weeks away from a database. We will have first protos in June. There
was concern about what to do if we found more problems with the test chip
after the changes are made.
ACTION ITEM: Steve Dollens and Keith Lofstrom will define mask
After changes are defined, Rev. B will be made. It will go through volume
production with an engineering lot of 10 wafers x 1500 chips/wafer; should
be completed sometime in August (June +8 weeks). We need to get the chips
in the queue. Mask changes will be done in 4 weeks. Another 4-5 weeks should
be allowed to go through fabrication. Mani asked to whom the chips should
be sent after they are made. Steve Dollens said Medtronics and Keith will
be the recipients. Bill Coombe at Medtronics will do whatever tests were
Steve Dollens will design and fab the evaluation board by July, 1996.
Mani will be the first user of the board. Mani is to give the final pin-out
of the parallel port and get the FIB part from Medtronic and Keith. Software:
Adam will be coordinating between Keith/Intellitech, due by July, 1996
(see viewgraph for more information).
All should report to Adam Cron by the end of September, 1996.
This is a follow-up to yesterday's debate on 1149.1/P1149.4 compliance.
To claim P1149.4 compliance, a chip must have:
1. 2 analog bus pins: AT1 and AT2 and switches.
2. ETAP (TAP + ATEST instruction + AMODE signal). ETAP is in the draft and AFUNC has been motioned in.
3. All pins comply with 1149.1, exceptions documented, i.e., simple interconnect test.
Adam Ley said "1149.1 is not per pin, period, as it stands today."
In other words, one can't say "compliance to 1149.1 except..."
It would require changes in 1149.1. We have already motioned in the rule
that every pin will have simple interconnect test. The issue is whether
we can treat 1149.1 as per pin (the answer is "no"). Mehdi suggested
"all digital pins comply with 1149.1 rules", which is a fact.
There were other suggestions to take out the third and fourth bullets and
just say "chip is 1149.1 compliant." But Adam Cron disagreed,
citing the need to address analog pins. Adam Ley asked to make the change
to "all analog pins have simple interconnect test capabilities, exceptions
documented," replacing "all digital pins comply with 1149.1."
Terry Junge then asked if there was a chip that's purely 1149.1 compliant
and we added an analog line to make power supply measurements, is it P1149.4
compliant? Ken said this is an ad-hoc measurement and is 1149.1 compliant.
Terry asked if he can put in one bus that he needs, but add the AT2 to
make it P1149.4 compliant even though AT2 will not be utilized. Ken replied
saying one would treat this as an ad hoc test under 1149.1; as long as
1149.1 requirements are met, one may go in the chip and do whatever needs
to be done. Terry said he would prefer not to treat it as ad-hoc but would
like to call it P1149.4 compliant. This would just be a subset of the bottom
example of Lee's viewgraph shown yesterday. Since Terry's example is a
special case, Ken said if there is a big demand for what Terry wanted,
then we will address it.
Two motions were on the floor (Bullets 1 to 3 have been motioned in
previous meetings; refer to viewgraph), the motions are for bullets 4 and
MOTION: All analog pins have simple interconnect test capabilities,
exceptions documented. Seconded. Yea: 11. Nay: 0. Abstention: 0. Unaminous
approval. Motion carried.
MOTION: All analog pins have P1149.4 parametric test, exceptions
documented. Seconded. Yea: 11. Nay: 0. Abstention: 0. Unaminous approval.
When does a pin become digital or analog? If a pin has 2 states, then
it is digital. Adam Ley said tri-state is not really a valid state. What
about inputs? Mani suggested looking up the IEEE definition of analog pin.
According to the P1149.4 draft, we have already settled on the definition
of a digital pin which consists of two discrete states.
1149.5 is a done deal. Nobody has anything to report on P1149.2.
Adam Cron stated he was happy with progress made in P1149.4 and 1149.1
this week. The issues are getting smaller. Adam and the WG thanked Seagate
for sponsoring the meeting.
Motion to adjourn: Seconded. Unaminous approval. Meeting adjourned.