11491149.4 Working Group Meeting Minutes October 1, 2003 ITC 2003 Attendees: Bill Aronson National Semi USA bill.aronson@nsc.com Arden Bjerkeli Asset Intertech UK abjerkeli@asset-intertech.com Jean-Louis Carbonero ST Microelectronics France jean-louis.carbonero@st.com Pete Collins JTAG Technologies UK petec@jtag.co.uk Ivan Duzevik National Semi USA ivan.duzevik@nsc.com Heiko Ehrenberg Goepel Electronics Germany he@goepel.com Andre Fidalgo ISEP Portugal avf@dee.isep.ipp.pt Ken Filliter National Semi USA ken.filliter@nsc.com Simon Guan Lokheed Martin USA simon.guan@lmco.com Graham Hollands 3Com Europe UK graham_hollands@3com.com Carl Jeffrey Lancaster Uni UK c.jeffrey@lancaster.ac.uk Tapio Koivukangas Nokia Mobile Phones Finland tapio.koivukangas@nokia.com Veikko Loukusa Nokia Mobile Phones Finland veikko.loukusa@nokia.com Charles Meyerson Medtronic USA charles.meyerson@medtronic.com Markku Moilanen Uni of Oulu Finland markku.moilanen@ee.oulu.fi Chuck Reid Guidant USA chuck.reid@guidant.com Teuvo Saikkonen Uni of Oulu Finland ts@ee.oulu.fi Juha Voutilainen Uni of Oulu Finland vouti@ee.oulu.fi Markku Walmsley Guidant USA mark.walmsley@guidant.com Jim Webster BAE Systems UK jim.webster@baesystems.com Working Group members Adam Cron Synopsys USA acron@ieee.org Frans de Jong Philips Research the Netherlands frans.de.jong@philips.com Adam Osseiran NNTTF Australia a.osseiran@teletest.org.au Ken Parker Agilent USA kenneth_parker@agilent.com Steve Sunter Logicvision Canada sunter@logicvision.com The meeting started at 3:00 pm Description Language There was considerable discussion about whether 1149.4 information should be coded in an analog extension to BSDL or to CTL. Ken Parker said that CTL is too new, and presently has insufficient industry support, whereas “everybody has a BSDL parser”. Adam Cron said that at a VTS WG meeting in May 2000, John McDermid presented a first draft of an analog extension to BSDL – denoted a “straw dog proposal” - it covered 95% of what could be a complete version. Ken Parker will follow up on this issue assisted by several members of the WG and some volunteers present at the meeting. Steve summarized that a BSDL analog extension seems most appropriate for describing the analog boundary test access and possibly some core access, and CTL seems most appropriate for describing the analog core access and possibly some analog boundary access. Ken said that users want a single file that lists both digital and analog pins. Parsers for BSDL already exist and could be adapted to accommodate 1149.4. Unmodified 1149.1 parsers will simply ignore the analog pins. A motion was proposed by Frans, and seconded by Ken Parker: the description of 1149.4 should be an extension to 1149.1 BSDL. All five WG members voted in favor. The WG will inform the IEEE of its decision to adopt BSDL as the 1149.4 description language. BSDL will have an extension for analog, similar to the extensions for 1149.6 and 1532. To follow up on this issue with volunteers, these minutes will be sent to the reflector with the dot4 URL (http://grouper.ieee.org/groups/1149/4/) and the WG meeting minutes of May 2000 in which analog BSDL is discussed ( http://grouper.ieee.org/groups/1149/4/min0500.html#language ) When the attendees were asked who would look at the analog extension proposal, 8 people raised their hands. Tapio noted that they need dot1 and dot4 because their boards are mostly mixed-signal. Pete said that he’s hearing lots of customer interest in dot4. Update on the standard Next year, likely before the next WG meeting, the published 1149.4 standard becomes 5 years old, and there is an opportunity to edit it before then. Editorial corrections to 1149.4 standard An email will be sent and include the list of editorial changes. A note in the minutes of May 2000 already mentioned these modifications – as listed here for convenience (thanks to Adam Cron): A note: Sample/Preload is one of the things that were revised in Dot-1. Page 45, the bits should be in a clear order. Change the picture instead of the table. Paragraph hard to read on page 56. The paragraph is about Vdd/2, the bias voltage and resistance. Ken said it might be worthwhile to have Steve and John take a look at that paragraph. Page iii: delete “This Standard…” Page iii: edit personnel lists Page 25, section 6.2.2: description of TBIC needs an edit (as follows): Change “- To the internal…” to “In addition, this switching structure allows the internal analog bus lines to be connected to the internal…” Page 69/70: Switch graphics for figures 48 and 49 Page 74, section 10.2.1: 2nd and last bullets: change “mode” to “node” Page 75, table 11: add lines SW7/8 (need exact lines) Page 76, section 10.2.2f: add f8 and f9 for Vg (need exact issue restated) Add a description of how to connect an ABM to a digital pin Comprehend new 1149.1 rule changes Figure/method to measure Rcom should be 10 ohms, not 1 Kohm. (Where is this figure/method?) Steve said he provided a descriptive note of how to connect an ABM to a digital pin (so that it meets 1149.1 and 1149.4 rules for digital pins). This is shown in an ITC’02 paper by Sunter et al. We will need to add a note to Rule 10.2.2 referring to the analog extension, when the extension has been created. We need to update 1149.4 to reflect the changes that were made in the latest version of 1149.1. Rcom must typically be << 10 ohms, not 1 kohm as it may say in the present version of 1149.4. New applications, and open discussion Charles raised a concern that if on-chip stimulus and response capture exists on-chip, and uses the analog buses, there are no rules governing this situation. Steve noted that the rule regarding internal scan chains not interfering with boundary scan measurements is the most applicable rule, and the other applicable rule is the one regarding 1% measurement accuracy. He said that being more specific than those two rules would be difficult, but welcomed suggestions. Steve noted that for deep sub-micron CMOS technologies, as was first noted several years ago by Matsushita, transistor leakage may limit the number of transmission gates per bus to around 30. This was one reason that the analog bus is permitted to have one level of hierarchy on-chip. Thirty transistors place an upper limit of 30x30 = 900 on the maximum number of nodes that can be accessed. To go beyond this, and to make layout more distributed and less of a star configuration, we could consider permitting more levels of hierarchy. Charles said his company was using only two bits per pin to save gate area, by omitting the D and C bits – only using the analog bus access bits. This permitted analog access and the ability to drive logic 1 and 0 (via each bus), but it prevent measuring impedance at the same time. Steve noted that using 2 boundary scan bits, with 4 latches would permit all variations and reduce boundary scan length – however it would require two boundary scan loads: one to set the digital state, and the second to select pins for analog access. Steve noted that the switches which deliver Vmin and Vmax to a pin are permitted to have an impedance as large as 10 kohm. If the pin must always have, for example, a 50 ohm load off-chip then the Vmin and Vmax switches are useless – we have no rule to address this. We should either say that the drivers are not needed for this case, or that the function driver must be used. Carl asked where the 1149.4 bandwidth limitation originated. Steve replied that the limitation comes from assuming use of near-minimal size transmission gates, each with 500 ohm resistance, one in the ABM and one in the TBIC to total 1 kohm, and a few hundred picofarads of off-chip bus capacitance. If analog buffers are used in the TBIC, the bandwidth can increase by more than an order of magnitude. Steve said that we should consider permitting ABMs to be used as an ATAP. It permits all existing switch combinations of the TBIC, but allows the same pad cells and boundary scan cells to be used. When this was proposed several years ago, it was rejected to ensure that the ATAP pins were used for only test. However, 1149.1 permits the use of a compliance enable pin which allows even the digital TAP pins to be used for non-test purposes. Charles asked whether an ABM could be used and documented for a power pin. These pins are normally listed as Linkage pins, and an ABM is certainly not required, but monitoring a power pin’s voltage can be quite useful. Presently, this would be described as internal access. Steve noted that we need a more efficient solution for differential pins. Presently, we require 4 scan bits per pin, and 8 bits per differential pair. It might be possible to allow all existing test capabilities with only 4 bits per pair whenever a fully differential ATAP is used (AT1, AT1N, AT2, AT2N). Differential is likely going to be a popular way to implement dot4. Steve (and possibly others) will investigate further. Considering a date for the next WG meeting, Adam Osseiran asked the attendees to raise their hand if they plan to attend VTS – no one raised their hand. Six raised their hands for DATE. Meeting adjourned at 4:40 pm.