|8:00am||Arrival and Introductions||Adam Cron|
|8:15am||Approval of August, 1998 Minutes||Adam Cron|
|8:20am||Potential New Officers||Adam Cron|
|8:35am||Review of August
Core Disconnect (CD State)
Chapter 9 Details
|10:30am||Follow-on Chapter 10 Requirements||Ken Parker|
|10:45am||Application of P1149.4||Chau-Chin Su|
|12:00pm||Adjourn for Lunch - Thank-you Synopsys|
|2:15pm||P1149.4 Status at Matsushita||Keith (Katsuhiro) Hirayama|
|3:00pm||Break - Thank-you Panasonic|
|3:30pm||Fig. 48 in D21||Steve Sunter|
|5:00pm||VSIA Update||Adam Osseiran|
|5:30pm||1149.1 Status||Adam Ley|
|5:45pm||Next Meeting||Adam Cron|
|Working Group Members||31|
|Total Subscribers on "esd" reflector||402|
|Companies and Other Institutions Participating||~290|
|John Andrews||National Semiconductor|
|William Aronson||National Semiconductor|
|Terry Borroz||Teradyne, Inc.|
|Dan Dandapani||University of Colorado|
|Frans de Jong||Philips Research|
|Keith (Katsuhiro) Hirayama||Panasonic|
|Jake Karrfalt||Alternative System Concepts|
|Adam Ley||Texas Instruments|
|Elbert Nhan||Johns Hopkins University|
|Adam Osseiran||Ecole d'Ingenieurs de Geneve|
|Jose Santiago||VLSI Technology|
|Mani Soma||University of Washington|
|Chau-Chin Su||National Central University, Taiwan|
|Dr. Michael G. Wahl||Universitaet Siegen|
|Brian Wilkins||Southampton University|
|Sean (Shoichi) Yoshizaki||Panasonic|
|Alex Zamfirescu||Alternative System Concepts|
|Prof. Edmond S. Cooley||Dartmouth College|
|Bob Gillis||GE Harris Energy Control Systems|
|Ad van de Goor||Delft University of Technology|
|Pilch Grzegorz||University of Technology, Poland|
|Ed McCluskey||Stanford University|
Adam said we had about 31 WG members. He kept getting e-mails from interested people. As of the day of this WG meeting, there were a total of 501 WG members and subscribers. He showed a graph of the addition of new members. This graph can be useful marketing information. There were also people that requested their names be removed from the list.
Adam said there were tiger team meetings in July and August. We worked hard during those meetings. Brian Wilkins said we got lots of comments for the draft last time and there were still issues to be resolved. Among them is the nagging differential I/O topic. Another issue that has come up recently – the "Reference" node. There were 10 or 11 comments related to this in the last ballot. There was apparently confusion over this. Some people didn't even have a good understanding or a solid background such as Ohm's law. Brian finally was able to put it all together, hastily. He had encountered problems with formats, software, printers, etc., but managed to turn the draft into a PDF file. Ken asked if this was D20 or D21 since the title said D20 but the header said D21. The answer is D21. Brian will correct the title.
Adam said he'd like to go over what had gone on between August and this ITC meeting.
Steve Sunter said we managed to resolve most issues. This is just to let everybody see if it all makes sense and if there are any additional comments. There are still a few more minor things that need to be worked on .
Steve showed a viewgraph (Fig. 7.4X1 on p.72): Basically the only new thing is the "CD State." It used to be called "High-Z State." Just a reminder: A pin is in CD state when it is not being driven by anything but may be connected to dependent sources.
In the table on viewgraph, the 2 R's in the upper left corner in the "CD" column were added. What the Xs mean is they are undefined. The designer has no constraints whatsoever with these Xs. He's not required to document all that stuff. This will fly with the differential I/O designers since they would have more flexibility. This results in symmetrical requirements. It's consistent with Dot-1 in that we can have differential inputs and an output. We'd just have to monitor the output of the receiver itself. It almost comes for free. John Andrews endorsed it. He said he likes this arrangement. Adam Cron said in Fig. 22 on p. 75, each pin is still delivering all the capabilities of an ABM. John said some circuits will reduce to the 2 lower R's in the table. Steve pointed out that with a 50 Ohm driven by a source low on either side, this situation qualifies as being a CD state since it's just a passive 50 Ohm resistor tied to a known rail or ground. This is an example of how to implement CD and VG simultaneously which should have no impact on the pin. Ken said a differential signal can be in the system mode or in the test mode. Some signals can be differential in system mode but are single-ended in test mode. What we're talking about here is correlated and uncorrelated signals. Ideally all pins are uncorrelated. But we can handle both uncorrelated and correlated signals with this scheme. Dot-1 doesn't have a CD state but has only a true high impedance state. Ken pointed out that Section 10.3 expands on that. There are no specific timing requirements for differential pins. Steve said all analog boundaries are updated at the same time and that differential pins are not distinguished from other types of pins. Brian asked about the Xs for undefined states. His opinion is that it should be a Rule that these pins be specified by the manufacturers for their particular products. Steve said we shouldn't do that. Keith said this would require additional circuits to be added that might add to the costs and it may be cumbersome. That's why now it's only a Recommendation. Keith said the only concern is to make sure these states are not those that would "screw up" circuits or otherwise result in unsafe conditions. So it stays a Recommendation that the manufacturers specify these "X" states.
SUMMARY: A new state called "CD" has been added. It's not just a high impedance state but may also include dependent sources.
Keith Lofstrom: In the August WG meeting in Colorado, the complexity of on-board and on-chip testing was presented. We should not unduly restrict on-chip circuits. The circuit diagrams for the integrated circuit chips discussed below are available from the appropriate manufacturer. Keith showed a diagram of the internal circuitry of the commercially available AD7524 8-bit multiplying DAC integrated circuit chip (Analog Devices). The chip has a "nasty" R-2R ladder architecture. It's a relatively common device. These chips are available with an internal feedback resistor because it matches with the other on-chip resistors in temperature coefficients as well as in value. Keith said we have to be able to handle real circuits like this. Another example is an NEC A/D converter with a large resistor network on-chip. Where do we draw the line on the residual elements? Keith'sviewgraph (VG5-Aug) shows 2 supplies and 1 resistor on chip. One thing not allowed in the current Draft is a resistor from pin to pin on-chip. That resistor is legal off-chip; so why not on-chip? We should allow for things like this. The designer has to document it in the CD-state. A resistor between 2 chips is allowed and can be handled by Dot-4. If it was off-chip, one would run into the same problem. We need to know how to describe it. Keith's viewgraph (VG3-Aug) shows 2 resistors on a chip which are not allowed but they really should be. Keith's vuegraphs (VG4-Aug) if we allowed the circuit in VG3-Aug, why not one resistor to a DC supply on one chip. Keith'sviewgraph (VG10-Aug) is a list of suggestions for handling the issue of complex and real-life circuits. Basically, we should allow on-chip networks involving many pins but forbid transimpedance circuits and negative value elements. We should also permit a buffer on-chip (VG5-Aug). We're not allowing this now but maybe later. On VG10-Aug, what's the meaning of "a linear combination"? It's simply any combination of simple L, C, and R elements. Fig. 44 in the Draft shows an example of a network modeled by simple elements, John McDermid pointed out. Ken asked if the term "combination" has an ambiguous connotation. It means no controlled sources, Brian said. Also, there should be no non-linearity in these simple elements. Keith said we do have a range of validity for these elements. Brian said on page 64 we need to show what combinations ARE allowed and what are NOT. Brian said we need some early references to this before we get to page 64.
On Keith's viewgraph (VG16-Aug), he had a proposed branch element that captures variations in resistance, voltage and current around design targets for currents and voltages. Some pin descriptions may need only one or 2 elements. For dc simple interconnect tests, the L and C's go away since they look like shorts and opens. Adam said the bottom line is we're defining a new "CD State" for Dot-4 pins. High-Z is mandated for Dot-4 pins but CD State is for analog measurements.
SUMMARY: Dot-4 should be able to handle real-life complex circuits other than simple interconnect and passive parametric measurement tests.
Ken Parker: In Fig. 50 on p. 109, one of the things we want to do is describe a pathway from node to node. We need a general model valid over a particular range of testing. Ken drew a viewgraph of such a model. He pointed out there is a series of impedances with a leakage current and an offset voltage across the nodes. He said if we requested a VL on the function pin, we're asking people to document it. These parameters make sure that you take into account the parasitics if you used a buffer rather than say a CMOS switch. We need a VL or a VH at that function node. We need to make sure we get those capabilities at the pin. The chart on p. 110, line 4, from AT1 to a function pin. Steve said it's well documented elsewhere. Steve said we could simply delete it. Steve and ken will look into this. Ken's discussion also applies to lines 5 and 6. Ken said this model should be good enough for VG. John McDermid suggested that we discuss this further. This leads straight to Brian's VG discussion. Alex Zamfirescu asked what range of validity is appropriate here? A voltage range of validity should be specified and not one for the current. Steve said we could always measure the voltage and it's generally easier than measuring currents. Ken's model is a start. Adam Ley asked if the Z element in VG1 is a complex impedance. Yes, it is. But we're talking about simple interconnect testing here. Ken questioned whether we were going to see anything other than a simple R. For VG, maybe we need a reactance (jw) in there as well (complex). So Z would just be R for simple interconnect testing. Adam Cron asked if this is clear in the writing. Steve said we could make a modification saying there should be no DC dependent sources but if some node depends on VDD it'd be fine since it's fixed and won't change. Adam said we need to make sure what ARE allowed and what are NOT in a CD-state.
SUMMARY: A generic model for node-to-node measurement over a valid measurement range is needed taking account into newly added features such as CD state and component non-ideality.
Ken said in the glossary, "residual elements" should be defined. Upon entering the CD State, there may be some residual elements to consider. In Fig. 51 on p. 114, there is an example of a residual element. When we look at the I/O pin, there's impedance at the pin. The only thing not shown in this figure is Rcom that may exist for ESD purpose. Rcom is described in Chapter 9. This is a generalization of what Keith was talking about. We're encouraging people to bring more and more components on-chip. This results in residual elements. The key here is we have not complicated the testing. These components are either on-chip or off-chip, Steve said. Ken said Table 11 on p. 115 shows how it should be documented for the circuit on p.114. The match/correlate column in that table helps in situations like R-2R ladders. This will allow you to note resistors that match. Steve said some companies might not want to publicize the circuitry. But we have to have a circuit diagram to do testing. Frans de Jong asked about the ABM and DBM. Keith had pointed out that it's not practically possible to make those resistors disappear. Frans said we should add a note in the Draft that says we should put all those residual elements in front of the ABM. In Dot-1, one can't put logic in between the core and the pin. What about complete isolation from the core? Should we put the Rcom in the figure? But Ken said there's a note in there that refers to Ch. 9 for this. Rcom will be discussed off-line. Brian said in Fig. 50 there should be a blue arrow in there since all voltages are referenced. Section 10.3 talks about residual components.
SUMMARY: Residual components should be clearly defined and described in the Draft.
Brian's VG discussion: In the VG figure in Draft D21, need a VG for reference for current and voltage measurements. Refer to the bottom circuit on Brian's viewgraph. Suppose we need to measure the voltage between 2 pins we would need a VG. What we require is it should be a constant voltage -- either ground or at a certain voltage. It doesn't really matter but it has to be constant. There is VG on-chip and another one off-chip on the board. The problem is that we have a "blue driver" (drawn by Brian) driven by an SL signal. We can force the driver to deliver a VL. Now the reference node is one on the driver connected to the external VG, and not the chip VG to the external VG. Brian has removed the note that said VG has to be a pin (removed from the definition of "quality voltage"). Ken said the range of validity of the model is also important
NOTE: VG function is not the same as the VG voltage. What reference quality does this VG have to be then?
John McDermid said there are 2 parts to this issue -- interconnect and parametric tests. To measure the voltage across the CUT, we don't care what that F2 voltage is. But to do an interconnect test, a VL test for example, we need a STABLE reference. We don't probe the F2 node but we probe at the blue vertical pin. Keith said there's a subtlety here. We may need a reference-quality VG value for the valid range of measurement. Brian drew on the bottom of the viewgraph F2 connected to VG through a near-ideal voltage source but it can be anything in general. The whole issue is whether we can save a switch by "cheating" using a quality reference from the supply of the blue driver. Alex asked where the return current would go. Maybe the buffer can't handle it. But John said we are not saying anything about what the path between F2 and the external VG should be. We have been debating this issue over e-mail for a few months now. The only requirement is that the current through F1 should be the same current through F2 to measure the voltage across CUT. Adam asked if there were any more questions on VG. No.
SUMMARY: There's a distinction between VG function versus a VG voltage. One important question about VG is whether it has to be reference quality.
Chapter 9: John McDermid gave a quick overview. Some changes were made after we read this 3 or 4 times. The biggest area of change is in Fig. 44 on p. 99 and forward from that point. It includes a leakage current, an offset voltage and others. The test current is 100 uA instead of 100 A (a typo as a result of translation of the software). These document and support the claim that what you're doing is correct. This shows how to do it. Steve has nothing else to add to that. In other words, we didn't change any rules but we put in sections on how to verify the circuits and a nice explanation of where they came from. What about a rule on verifying VG. Brian said there was an e-mail that mentioned it. It can be made into a rule. Rule 9.4.3 g should be connected to a Rule "h." Steve said we have a rule on p. 102. It's Rule "a" instead of Rule "h" at the bottom of p. l03. Rule "n" is the so-called "1% rule." Your measurement errors should be less than 1%. In chapter 9 we didn't add any rule besides that one. Rather, we made clarifications responding to comments from the ballot. Steve will get to that rule later.
On p. 95, there's a drawing error -- 2 missing power supplies on the buffer. We need to add them to the diagram. It's not realizable unless there is a return path to the buffer. Keith's point is with the ac voltage, the current needs to flow through it and back to the power supplies (missing from figure). Need the power supply pins connected to sources added to the buffer (Brian's action item).
Fig.48 is blank (Brian will fix that). John and Steve have new 1-5 and new 6-7, respectively. New figures will be added to the Draft. Alex asked about the Iout formula underneath Fig. 40. It should be "–" and not "+" in the formula. This is the one to verify the 1% rule. We will need another figure -- Fig. 48a. Steve will draw the figure.
SUMMARY: Typos and errors in the various figures in Draft D21 were pointed out and they will be corrected. Some of the rules in Chapter 9 were discussed and clarified.
The purpose of his experiment is to derive an intrinsic response extraction algorithm for the removal of parasitics and extend external components measurements.
Viewgraphs on the test circuit, simulation model and test conditions were flashed on the overhead projector. These were then followed by viewgraphs on the parasitic effects, measurement plots with and without parasitics. In the Metrology viewgraph, every module has the same intrinsic response. The measurement procedure, calibration, measurement, extraction were then discussed. He showed how the intrinsic response (IR) extraction was done. The convolution process was also described. Direct loop-back for parasitic effects measurement as well as buffered loop-back were presented. In the calibration process, a calibrated equation was derived. Next, Chau-Chin showed a Dot-4 test cell, some test and simulation results, and switching device modeling circuit. Steve asked whether one of the plots shown were results with just the n-channel Rds on. He reasoned that If both p and n were turned on, we'd get the shape exhibited in Fig. 49 of the Draft.
More test results, SPICE simulation data were presented. Signals with different delays and rise times have different responses. The extracted response is about the same for the 5 different test signals with various rise and fall times. The test results from real measurements were shown. Chau-Chin showed a Test Setup viewgraph.
Test results showed (with an ideal input) the calibrated, ideal and real responses. The horizontal axis is time in us units on the plot. For a 10 us and 20 us signal, the responses are essentially the same.
To recapitulate, an algorithm to extract intrinsic response for analog measurements was presented. In Dot-4, a parasitic measurement method with use for an on-chip buffer was proposed. The algorithm was simulated using SPICE and test data were obtained from real measurements. This scheme can reduce instrument complexity and alleviate constraints on test equipment.
The test environment is MNABST-1. For parasitic effect measurement, various switching resistances of 100 to 6.4k ohms were measured. For different frequencies, different responses are expected. On the Test Environment: Experiment Overview viewgraph, another buffer was inserted on the bottom right to the second ABM at the bottom. The entire circuit can be treated as one loop. An HP16500 tester was used for the experiment. Adam asked whether it would still work if we connected AB1 to AB2. The answer is no. The impedance is not the same as the test circuit. That's why a buffer with a large input impedance was inserted. Keith said we don't require but do allow for a high-impedance input and low-impedance output. Keith said to implement this, we'd need to add switches which are not Dot-4 switches. Steve said it doesn't have to be an ideal buffer but it should have a high-impedance input and low-impedance output and use that as the "ideal" response. There's no buffer to go from AT1 to AT2. We don't have a calibration between 2 busses. The extra buffer is an impedance isolation device and we don't need it to be ideal because its response will be canceled out anyway. The key is you need to look at the response through the same buffer. Viewgraphs of the laboratory setup and the circuit under test were displayed. Three different impedance values were used in the measurements – 100, 400, and 1,600 Ohms with their respective nominal and worst cases shown. For the first 2 impedance values, the responses with and without intrinsic response extraction were practically identical while the extraction made a big difference in the 1,600-Ohm case. Specifically, the extraction eliminated the disparity between the responses with and without extraction. The technique also improved the DSNR performance. At low frequencies, the extracted and non-extracted SNR were similar. For the 1,600-Ohm case, there's limitation as to how much parasitic effects can be tolerable. If those effects were very dominant, then there's really no way to recover the ideal responses since lots of details would be lost. If the time constant is too large, it can't be done either. A minimum of 20 dB SNR is desired. One can go up to 8 times the frequency of the square wave to check the natural frequency. Steve pointed out that we couldn't rely on the 3SOA buffer in the "Buffered Loop Provision" viewgraph because there could be things connected to it.
SUMMARY: An intrinsic response extraction algorithm was presented and test results verifying the technique were obtained and discussed. More details may be obtained from the Chau-Chin Su's ITC paper.
Refer to VG2 general descriptions of the chip are 0.25 um CMOS, 204 pins, 387k gates, 2V and 3V operation. Dot-4 Instructions for this chip are also listed. Viewgraph VG3 shows the frequency response of the analog test bus exhibiting a 10 MHz 3-dB roll-off. The resistive impedance of analog switches were shown to be temperature dependent and varying over the operational voltage range. The pins shown have ESD protection provisions. Precautions were taken to protect the device from operator errors. Refer to viewgraph VG4. A core disconnect switch was shown. Implementation with 2V and 3V power supplies was displayed. Level shifters were used. All digital stuff is 2V, and analog 3V. This is a practical example of Dot-4 implementation.
SUMMARY: Matsushita has mass-produced consumer products using a data-compression chip that is Dot-4 compliant for test purpose. Early results looked promising.
The other rule we should add is in Fig.48a. This scheme will verify that AB2 doesn't drain too much current. Leakages and other parasitics are all lumped into this rule.
We need a corresponding rule for a VG pin. Now a 100uA current is injected through the 1000ohm resistor (middle diagram of the viewgraph). The 1% error rule also applies here. This is just verifying you didn't hang something at the VG pin and generated too much noise over the bandwidth of the measurement range. Brian was still concerned about the diagram. There needed to be some constraints on the duration of measurement to account for drifts since we can't have a differential voltmeter across the resistor. We can only measure one node of the 1000-Ohm resistor at a time, that is, sequentially. We require that VG be stable during the time we are measuring the voltages at the nodes of the resistor. What Brian was concerned about is if there was a "red" supply at the VG pin (see the diagram). Keith said the drawing is not correct. It could be another chip that's connected to the other side of the resistor.
Keith drew the Rdrift in the diagram. When first measuring the node where the 100uA current is applied, Rdrift is 1kohms, but during the time we close the switches to do the other measurement, Rdrift could change to 2 kOhms. Steve said we want to measure a SINGLE function pin. We're giving a metrology of how to determine the reference quality of the VG pin. We have to say the drift of the VG voltage must be less than 1%. We have to measure the voltages of the 2 nodes of the resistor one at a time. We can't do a simultaneous measurement of the voltage across the resistor. Keith said we couldn't measure in Dot-4 a differential voltage. But we have to do it with 2 single-ended measurements and subtract them from one another. Keith said maybe we should take the 1000-Ohm resistor out and it's easier to explain. Adam Ley asked why make 2 measurements. Why not just make one and say it can't drift more than 1%. Keith didn't believe we can say the measurements have to be made in a certain amount of time. Ley said the reason for that resistor is to make sure we know what voltage range we're talking about. The measurement error of 1% is for the 1000-Ohm voltage. For a specific load, one should be within 1% of the 1000 ohms. For a 1Mohm resistor, one could be out by anything at all. Steve then drew a blue circuit at the bottom of the VG5. We'll use the blue diagram. The voltage at AT2 has to be within 100mV over a specified duration of time (to be determined). We're measuring an AC voltage. Keith didn't want to specify timing since there are other factors like environmental, etc. to be taken into account.
Right now there are no time constraints on either Fig. 48 or 48a yet. John McDermid said we not only have to be concerned with the stability of the AT2 but also the voltage range constraint specified back in Chapter 10. We have to make sure switch resistances are suitably low. Steve asked if everyone is comfortable with the blue circuit. The only thing left to determine is the amount of time for measurement. Keith said we shouldn't give people "wiggle room." Good design will stabilize out after a specified amount of time. Bad designs self-heat. It's the designer's choice to keep the drifts down. What Keith was proposing is what we've discussed. John said to make it a 1-second measurement time instead of infinite. Stability has to be 100mV within 1second (maximum). Anything other than 1 second needs to be documented. Adam Cron said still, documenting it will not take care of problem. Let's stick with the 1-second rule, Mani said. Frans said heating up the chip is still a concern. Adam Ley said there's resistance in the path from the VG pin to the function pin. The Rdrift should be made as small as possible. The consensus seemed to be that this is the test circuit (blue) and the test time is 1 second. Also it's beneficial to keep the resistance small.
There are currently 7 Developing Working Groups (DWG) active within the Test Developing Working Group (TDWG). Among the 7 are a mixed-signal group, an on-chip bus group, and a manufacture-related test group.
Steve said it's been coded that Dot-4 is going to be the way to do mixed-signal testing on these VSIs. The European Cad Standardization Initiative (ECSI) asked Adam Osseiran to talk about the Alliance at this Dot-4 meeting.
The objective is to identify existing standards to assemble virtual components and to provide documents to member companies with VC conformance descriptions. VSIA does NOT define new standards. The time frame is June, 1999. Adam showed a viewgraph on TDWG members and chairs. Another viewgraph explained VC's test similarity to BS. VC faces the same problems as chips on board.
The scope of the TDWG is to identify existing test standards. The plan timeframe is 1/98-6/99. There are 2 task forces for the TDWG: test data interchange format and guidelines for VC providers.
A document just came out last month (September, 1998) with meetings held every week. The 2 task forces were involved in the document development. Dan Dandapani asked if we could get a copy of that document. Adam said that only member companies have access to the document. For non-members, a signed non-disclosure is required to get a copy.
The scope of specifications involves 2 phases. Phase 1: The 2 task forces finished. Phase 2 document planned for mid-1999 will cover the transfer of similar information between the VC integrator and the manufacturing test engineering function. We're now in between phases 1 and 2. Adam Cron asked what's the value of VSIA. VSIA chooses in some cases competing standards for the same thing. But VSIA is trying to set up, Adam Ley said, a framework for VS providers what information to include in their products. Wherever possible, VSIA uses existing standards. So you can do comparisons. To allow you to put things together in VC's and if 2 VC's are VSIA-compliant, you know they will talk to each other and won't be stuck with differing formats and incompatibilities.
SUMMARY: VSIA was discussed. Possible implementation of Dot-4 standard was proposed.
Adam stated that a few incremental drafts were recently produced. The latest is the October 5th version. Basically, we have the core revisions in place (Chapters 12, 13, and 14) specifying boundary scan registers. Some issues like residual elements and others have not been incorporated into Dot-1 revisions yet. There have been issues brought up like whether cells are required at analog pins. The current version of Dot-1 says that you SHALL have a cell at analog pins. As far as the timetable goes, maybe we'll have a better idea when things are wrapped up for Dot-1.
The Dot-4 BSDL should be synced with the Dot-1 standard. Adam Cron said Draft D21 was revised based on the existing Dot-1 standard and may not necessarily take into account what revisions would be made to it.
One last note from Adam Ley: The Dot-1 draft has been circulated to some members of Dot-4. CJ Clark has made it possible for all Dot-4 members to access the draft on the website. We're welcome to review the draft.
Steve asked what Dot-1 is doing with regard to differential I/O pins. Adam Cron said the current Dot-1 draft that's circulating mandates a "Whet-Cell." Should we, Dot-4, support this mandate or go with a recommendation. The motivation for this discussion is that Colin Maunder sent out a response that with an unproven technology like "Whet-Cell," should we mandate it in Dot-1? Adam agreed with Colin. Keith also didn't want a mandate on the unproven and unverified Whet-Cell. Let's just make it a recommendation and say maybe in the future we'll mandate it. We don't want people to hang a Dot-1 cell on analog pins simply to be Dot-1 compliant.
Adam Ley drew on viewgraph VG6 analog and digital drivers and receivers. The color blue means "optional." Red means "mandated." The square boxes represent DBM's.
A second level buffer is added (the small buffers drawn). These DBM's have to be "observe only" and are mandatory (required at the pins). The input DBM's are "control and observe." This applies only to drivers (on the bottom of the VG6). For the receivers, in EXTEST we can observe at the differential voltage applied at the input and therefore we can observe the results at the output. John Andrews asked if these are always all in the boundary registers (DBM's). On the receivers, for EXTEST, the control function in the input DBM's will be disabled. Adam asked whether there will be any new BSDL ramifications. We're only specifying the same bag of cells we already have and providing some new cases for them. The core BSDL descriptions won't change. Frans asked if we code the blue cells as part of the internal cell. Probably yes. For EXTEST, the blue cell can be internal. For the lower case (on the bottom of VG6), we'd need to define the relationship between the input DBM and the output DBM's.
Previously, this would have been an analog-to-digital interface. Basically, we're saying in the language of yesterday's Dot-1, all differential receivers are essentially analog in nature and we'd treat the pin inputs according to the rules we had for analog. For drivers, there are 2 cases. One is where one separately has provisions for the output of the drivers. The other is the opposite case. Ley asked how well this correlates with the current Dot-4 draft. Cron said we'll specify "control and observe" on all pins. Ley reminded everyone that Dot-4 is a superset of Dot-1 in differential I/O's.
In the Table of Fig.50, Dot-1 only requires the L and H columns while Dot-4 requires all 4 columns.
Adam Ley said the residual components can complicate things, even in simple interconnect tests. We still need a way to describe the residual components in simple Dot-1 interconnect tests. Steve said we could use a functional driver to do the interconnect tests and if we don't want to, we could use Dot-4. John Andrews said in Fig. 23 there's a differential comparator at the outputs mentioned in Dot-4 but not in Dot-1. The function of that comparator is described at the bottom of p. 72, Rule b. That's a new rule which did not exist in D18. John said the control part of the inputs to analog and digital receivers should be made optional because it could be challenging to implement. Ley said it's optional.
SUMMARY: Adam Ley updated the WG on the Dot-1 standard revision status.
Please get comments out as soon as we can. We'll give IEEE a good paper copy of the comments, resolutions, and letter – the entire package. Keith asked if the IEEE requires resolutions be done in a WG meeting.
Suppose REVCOM says something? No, they won't, Adam Ley said, at least with regard to the technical contents. They're most likely going to "rubber stamp" it.
Keith said the next thing on our agenda is marketing it.
Brian Wilkins said we need to make some rules about residual components. We should incorporate the residual components. Keith and Steve should get together on the residual. We need to say something like what we can leave and what we can't leave in chapter on p.64. we need a couple of sentences on what rules there are as far as the residual components. We'll need boundaries, limits when we get into the rules. 3 or 4 little rules on that.
Steve summarized the changes to be made to D21:
Keith was concerned that people may implement what's in Fig. 40 and find it doesn't work.
John Andrews motioned (and Keith seconded) that Fig. 40 be removed. Discussions. Terry Borroz said if we put too many possible ways we can hook up pins, then people will come up with circuits that cannot be tested. Another thing is that unless you are sure something can be implemented, you don't publish it. Steve said since this circuit is not on-chip, there is no way to do "bad" things to a circuit. Steve didn't want it removed. John McDermid had no problems with removing it. Keith was concerned that this is a poor way of delivering a current to a pin. Steve said we at least need to show people how to do it. Keith said any chip designer could design a circuit to deliver the 100-ua current. Adam asked why we need to show this. Keith didn't agree with the reasoning that this is the only simple way to deliver a current. Steve said change it to "a way." Steve, John and Keith should come up with a replacement circuit (a better way) to deliver a current. Steve said this is the Norton equivalent way and the next Figure shows the Thevenin method. Michael Wahl suggested it be left as a recommendation. Should we be showing people how to design voltage or current sources, he wondered.
The original motion to remove Fig. 40 was aborted. A second motion was initiated instead.
Motion: Steve, John and Keith will redo Fig. 40 which will be kept in the Draft in a modified form. Seconded. Motion carried.
One new member at this meeting: William Aronson who will become a member at the next meeting. This was his first.
Status of Dot-4 WG:
Brian will update the member list toward the beginning of the Draft. Individuals that are current on the publication will be listed. There were members that had been removed in the past. The rule for becoming a WG member is 2 out of 3 consecutive meetings attended. Members missing WG meetings for 2 years would be subject to removal. The meeting minutes will show who have been here the past 2 years. We have been real lenient in removing people.
Steve initiated a motion.
Motion: The names of those individuals listed on p. 2 of the Draft who has not attended WG meetings in the past 2 years including the ITC meeting 2 years ago will be moved to page 3. Seconded. Unanimous approval.
It all depends on what we get on ballot returns. The next meeting could be when we're going to elect new chair.
Suggestions for the time frame for the next meeting are as follows: