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IEEE Std 1355-1995
Standard for Heterogeneous InterConnect (HIC)
(Low Cost Low Latency Scalable Serial Interconnect)
(aka ISO/IEC 14575 DIS)

Welcome to the home page for IEEE 1355 (H.I.C.)!

For further and more frequently updated details of the IEEE 1355 standard, please access the 1355 Association web page http://www.1355.org

Index


Status and ordering

This standard is now a fully approved IEEE Standard:- IEEE 1355-1995 Heterogeneous InterConnect (Low cost, low latency, scalable serial interconnect for parallel system construction). Copies of the final specification are available from the IEEE Standards Department. For full details see IEEE Standards Ordering Information. The same specification is also being carried forward as an International Standard as ISO/IEC 14575.


Overview

IEEE 1355 specifies the physical media and low level protocols for a family of serial scalable interconnect systems. The speeds and media range from 10 Mbps to 1Gbps in both copper and optic technologies. Various of the specifications in IEEE 1355 are optimised for chip-to-chip, board-to-board, rack-to-rack or intra-office communications.

The standard specifically aims to allow low cost and highly cost-effective simple implementations, and yet support scalable performance. This is achieved by a simple line protocol that can be implemented in as few gates as a UART, and by a simple packet protocol that can be used to make routing-switch chips to provide low latency wormhole routing. The cost, as with UARTs, is very low. Performance of a network with these routing switches scales with the size of the network, while retaining conservative and economical link speeds.

The range of speeds and distances covered by the 1355 standard may seem to be covered by alternative standards based on a logical bus or ring topology. Such topologies can only claim scaleability by requiring faster nodes. The 1355 standard on the other hand, has demonstrated scaleable performance from one to over a thousand nodes.

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Scope and Purpose

Scope

The scope of this standard is the physical connectors and cables, electrical properties, and logical protocols for point to point serial scalable interconnect, operating at speeds of 10-200 Mbit/sec and at 1 Gbit/sec in copper and optic technologies (as developed in Open Microprocessor Systems Initiative/Heterogeneous InterConnect Project (OMI/HIC)).

Purpose

The purpose of this standard is to enable high-performance, scalable, modular, parallel systems to be constructed with low system integration cost; to support communications systems fabric; to provide a transparent implementation of a range of high level protocols (communications (e.g. ATM), message passing, shared memory transactions, etc.), to support links between heterogeneous systems.

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Historical perspective

This Standard has been developed to make it possible to integrate several communications ports onto a single processor or controller chip, instead of needing several chips per communications port. It recognises the move in both existing and new standards for packet-switched communication across a switching fabric, instead of each having over a shared bus. It brings to these the minimum necessary protocol to achieve results, offering massive simplification over protocols that needed to be evolved for switching.

The work behind the standard was supported by a number of ESPRIT projects which funded STMicroelectronics and Bull as technology providers. STM completed the IEEE standardization process but, shortly after completion of the funded projects, they announced the withdrawal of all products based on the standard.

The users of the standard have rebounded from the setback and have taken advantage of the simplicity of the protocols to produce alternative sources of supply.

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Speeds and Media

The physical layer may be implemented in a number of different technologies, identified according to signalling convention, transmission medium, and maximum operating speed. These technologies are summarised as follows:

Table of speed, media and distance specifications

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Protocol stack

Whilst different electrical or optical signalling systems and encodings are used for each medium, the character encoding in each case allows for 256 "data" characters plus control characters. The control characters are used for a flow control scheme which operates at the "exchange layer" - the layer above the character layers, and are also used for delimiting packets in the packet layer. The packet layer is the highest layer defined in IEEE 1355, and is common across all the speeds and media. It defines the packet format in terma of a header, payload and an end-of-packet marker. The interpretation of the header and of the payload is application dependent.

IEEE 1355 protocol stack

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Brief rationale

The construction of high-performance systems with parallel I/O demands a fast, low-cost, low-latency interconnect. It must be fast and low-latency, otherwise it will be the limiting factor in system performance, and it must be low-cost, or else it will dominate the system cost. It must also scale well in both performance and cost relative to the system size, otherwise highly parallel systems will be limited in performance or too expensive. Existing standards do not meet these criteria, either because they are designed for communication over long distances (which incurs high costs), or because they aim at the extreme of currently achievable performance (which again increases costs), or because they are based on a restricted model such as a bus, which limits overall performance and scalability.

The IEEE 1355 standard protocols hierarchy are intended to address the problem of reliable, efficient, low-latency communication within high-performance concurrent systems, and communication between systems over limited distances. The emphasis is on a low cost-per-port to allow high levels of integration, and high system performance from concurrent network fabrics built with multi-way routing devices.

A detailed rationale, comparing the requirements for parallel systems interconnect with, for example, those for parallel communications systems (Telecoms, LANs, etc) is given in IEEE 1355 Rationale. Return to index


IEEE 1355 Tutorial

This tutorial presentation is available in pdf (Adobe Acrobat) format. It was prepared some years ago by the chair of the P1355 working group, Colin Whitby-Strevens, and is still a valuable explanation of the standard and the technology the standard enables. Additional information, some simpler than this tutorial, some with more detail, can be found on the 1355 Association's web site. comprises the following files:

  1. An introduction and overview (19 foils)
  2. A rationale (8 foils)
  3. A description of DS-SE and DS-DE links (10-200 Mbps copper) (6 foils)
  4. A description of TS links (250 MBaud optic) (4 foils)
  5. A description of HS links (1GBaud copper and optic) (4 foils)
  6. The exchange layer flow control and the common packet layer (8 foils)
  7. The use of 1355 to build interconnect networks (21 foils)
  8. Implementations and applications at the macrocell and chip level (24 foils)
  9. Implementations and applications at the board and system level (23 foils)

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Backplane turbocharging standards

Two "application standards" of IEEE 1355 are being developed to standardise the use of the HIC technology for providing extra bandwidth across an industry standard backplane.

The first, which has just received final approval, is ANSI VITA 13-1995 for the VME backplane. This specifies the pinouts for up to 8 DS-Links on the P2 connector for each VME slot - providing in excess of 300 Mbytes/sec bi-directional per-slot bandwidth. The specification does not specify any particular topology for the inter-slot connections, but leaves this open for competitive differentiation. This allows, for example, both fixed topologies and "active backplanes" incorporating dynamic packet routers. Additional flexibility is possible through the use of such routers on the VME cards themselves. Further details of the VME standards can be found from the VITA standards organisation.

The second is IEEE P896.11 for the new Futurebus 95 specification. This specification proposes the use of both DS and HS links on the P1 connector. The original proposal was based around Futurebus+, but, since the new Futurebus95 is already including DS-Links as an interrupt bus and secondary data bus, attention has switched to this specification. Work is at an earlier stage.Return to index


See also

The 1355 Association exists to promote the 1355 standard and to support its users and producers.

The OMI web page contains full details of the results of the OMI/HIC project including contact points for sources of products and technology. From the home page, click Projects and look for HIC, 1355, PUMA, Macrame or Arches.

For more information on other IEEE standards see IEEE Standards Department. For more information on ISO/IEC standards see the International Standards Organisation, the International Electrotechnical Committee and the IEC technical committees. The work of standardising ISO/IEC 14575 is being carried out by JTC1, SC26 (Microprocessor systems). For more information on VME standards see the VITA standards organisation.

The OMI/HIC Project was supported under the European Strategic Programme in Information Technologies (ESPRIT) as part of the Open Microprocessor systems Initiative.

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Colin Whitby-Strevens was chairman of the IEEE P1355 working group and was the original author of these Web pages. The pages have been updated by Paul Walker, editor to the 1355 Association.

Last updated: 30th October 1998