IEEE P1394B PHY-LINK Electrical Interface
The 1394b interface uses impedance-matched reflected-wave switching. Because of this the drivers’ most critical operations occur at less than full swing. Output characteristics are specified accordingly.
|
Symbol |
Description |
Typical |
Minimum |
Maximum |
Units |
|
VDDQ |
I/O Supply Voltage |
NA |
1.65 |
3.6 |
V |
|
Z0 |
Path Impedance |
NA |
50 |
75 |
Ohms |
|
CIN |
Input Capacitance |
4.0 |
3.0 |
5.0 |
pF |
|
VOH |
Launch Voltage (H) |
0.50 |
0.45 |
0.55 |
VDDQ |
|
VOL |
Launch Voltage (L) |
0.50 |
0.45 |
0.55 |
VDDQ |
|
VOT |
Output Measurement Point |
0.25 |
NA |
NA |
VDDQ |
|
ZOH |
Output Low Impedance |
NA |
NA |
75 |
Ohms |
|
ZOL |
Output High Impedance |
NA |
NA |
75 |
Ohms |
|
VILDC |
DC Low Input Voltage |
NA |
0.45 |
0.50 |
VDDQ |
|
VIHDC |
DC High Input Voltage |
NA |
0.50 |
0.55 |
VDDQ |
|
VILAC |
AC Low Input Voltage |
NA |
0.30 |
VILDC |
VDDQ |
|
VIHAC |
AC High Input Voltage |
NA |
VIHDC |
0.70 |
VDDQ |
|
ICL |
Input Clamp Current |
NA |
7.0 |
NA |
mA |
|
VCLH |
Input High Clamp Voltage |
NA |
VDDQ |
VDDQ+300 |
mV |
|
VCLL |
Input Low Clamp Voltage |
NA |
-300 |
0 |
mV |
|
VCLM |
Mean Clamp Voltage |
0.5 |
0.45 |
0.55 |
VDDQ |
|
VEXT |
External Signal Amplitude |
NA |
0.60 |
1.60 |
VDDQ |
|
VK0H |
High Keeper Voltage (quiescent) |
0.80 |
0.75 |
0.85 |
VDDQ |
|
VK0L |
Low Keeper Voltage (quiescent) |
0.20 |
0.15 |
0.25 |
VDDQ |
|
VKH |
High Keeper Voltage |
NA |
0.75 |
1.10 |
VDDQ |
|
VKL |
Low Keeper Voltage |
NA |
-0.10 |
0.25 |
VDDQ |
|
VKLM |
Mean Keeper Voltage |
NA |
VILDC |
VIHDC |
Table 1: Electrical Parameters
|
Symbol |
Description |
|
VDDQ |
I/O Supply Voltage of the DUT |
|
Z0 |
Path Impedance exclusive of lumped capacitances at line end. Devices are required to |
|
CIN |
Input capacitance: point-load-equivalent capacitance of an input. This is exclusive of distributed capacitance at Z0 |
|
VOH |
Output High Launch voltage: the output voltage of a HIGH-state driver into a grounded resistive load of magnitude Z0 |
|
VOL |
Output Low Launch voltage: the output voltage of a LOW-state driver into a resistive load of magnitude Z0 to VDDQ |
|
ZOH |
Output High Impedance: the dynamic impedance of a driver (di/dv) at VOH |
|
ZOL |
Output Low Impedance: the dynamic impedance of a driver (di/dv) at VOL |
|
VILDC |
DC Input Low Threshold: Input voltages less than this are guaranteed to NOT cause the input to change state to HIGH. |
|
VIHDC |
DC Input High Threshold: Input voltages greater than this are guaranteed to NOT cause the input to change state to LOW. |
|
VILAC |
AC Input Low Threshold: Input voltages less than this are guaranteed to satisfy timing requirements for input LOW. |
|
VIHAC |
AC Input High Threshold: Input voltages greater than this are guaranteed to satisfy timing requirements for input HIGH. |
|
VCLH |
Input clamp test points. Input clamps must hold the input voltage to VCLH or less in response to an input current of ICL and to VCLL or more in response to an input current of -ICLAMP. |
|
VCLL |
|
|
ICL |
|
|
VCLM |
Mean Clamp Voltage: Clamps must be symmetrical. VCLM is the arithmetic mean of VCLH and VCLL for ICL between ICL(MIN) and ICL(MAX). |
|
VEXT |
External Signal Amplitude: The peak-to-peak amplitude of an AC-coupled external square-wave source (at impedance Z0) which the keepers must accomodate. |
|
VK0H |
High Keeper Voltage: the Thevenin output voltage of the HIGH-state keeper in the absense of external signals |
|
VK0L |
Low Keeper Voltage: the Thevenin output voltage of the LOW-state keeper in the absense of external signals |
|
VKH |
High Keeper Voltage: the HIGH-state keeper output voltage when tracking external signals. |
|
VKL |
Low Keeper Voltage: the LOW-state keeper output voltage when tracking external signals. |
|
VKLM |
Mean Keeper Voltage: Keepers must be symmetrical. VKM is the arithmetic mean of VKH and VKL for VEXT between VEXT(MIN) and VEXT(MAX). |
Table 2: Description of Parameters
Interoperability between CMOS process generations can be accomplished in several ways. The cleanest is to use the same supply voltage on both sides of the interface. 1394B requires this for directly connected PHY-LINK pairs. It may also be used with isolated pairs, even across process generations, if the I/O system on either side is voltage-agile. Where this is not a viable option (as for instance with galvanic isolation and the high cost of adding an additional isolated supply) it is also possible to mix logic across a single generational gap.
The standard supply voltages for currently common process generations have been defined by JEDEC as:
|
Nominal |
Minimum |
Maximum |
|
|
3.3 |
3.0 |
3.6 |
|
|
2.5 |
2.3 |
2.7 |
|
|
1.8 |
1.65 |
1.95 |
|
Table 3: JEDEC-Standard Supply Voltages
To span a generation, the higher-voltage interface must accept signals swinging approximately 60% of the receiver’s supply (e.g. a 2.7v receiver and a 1.65-volt driver.) Similarly, the lower-voltage receiver must tolerate being driven by a source 1.6 times its supply. Since the 1394B PHY-LINK interface is source-synchronous switching symmetry is important. The requirement for symmetry accounts for much of the complexity of the adaptive I/O. Of course, maintaining symmetry with voltage-agile I/O circuits isn’t trivial either.
When a high-voltage source drives a low-voltage receiver, the receiver must operate in two main modes. Following a long quiescent period, the receiver has established a node voltage of VK0L or VK0H and transtions start from these points. Immediately following another transition, the receiver has established a node voltage of VCLH or VCLL and the transition starts from there instead. This causes a shift in threshold crossing. The magnitude of the shift is approximately VK0L-VCLL; for a 1.65v receiver this will be about 713mV, or almost 31% of a 2.3v driver’s output swing. This introduces as much as 0.25*tR in clock-data skew, which must come out of the timing budget.
Changes to the line state sequence on quiescence may prevent this.
In extreme cases, a 2.7v receiver must operate reliably when driven by a 1.65v source across a galvanic barrier. If a conventional bus-keeper mechanism is used to bias the receiver, the quiescent state could be ground. The first HIGH transition would take the input to 1.65v, less losses and noise, while VIHAC is 1.89v. Oops. In fact, VIHDC is 1.485v, which leaves only 165mV of noise margin. This is not a formula for reliable high-speed switching.
To avoid this the 1394b mixed-voltage mechanism uses an adaptive restoration mechanism. The (very) long-term quiescent line state must be at least 0.15* VDDQ. This guarantees that the initial transition drives to at least 0.75* VDDQ, which is in excess of VIHAC by 0.05* VDDQ. (In other words, barely.)
Note: No attempt has been made to protect the stubbornly clueless from the appropriate consequences.
The ideal clock/data relationship is quadrature, since it allows the clock to change state when the data lines are quiescent (thereby keeping at least ONE signal well-behaved.) In a nominal 5000 ps Unit Interval that leaves 2500 ps each for the setup and hold processes. A conservative design budget for these would include:
|
On-chip Clock Skew |
50 |
ps |
|
Cycle-to-cycle Jitter |
50 |
ps |
|
Flip-flop rise/fall asymmetry |
100 |
ps |
|
On-Chip Source Routing skew |
50 |
ps |
|
Intrinsic Driver Skew |
50 |
ps |
|
Driver Skew (SSO, Rise/Fall, etc.) |
1000 |
ps |
|
PWB Route Skew |
100 |
ps |
|
Input Asymmetry (assume 1000ps rise) |
100 |
ps |
|
On-Chip Receiver Route Skew |
50 |
ps |
|
Flip-Flop Setup/Hold Time |
150 |
ps |
|
Total |
ps |
Table 4: S1600 Timing Budget
This leaves a reasonably comfortable margin of 800 ps.
|
Symbol |
Description |
Typical |
Minimum |
Maximum |
Units |
|
VDDQ |
I/O Supply Voltage |
NA |
1.65 |
3.6 |
V |