The "CAD-to-Test" flow today is filled with many different formats for test information. Different formats exist not only for the interface between CAD tools and IC vendors, but also for the interface between those vendors and Automatic Test Equipment (ATE).
This variety of formats has created a test environment of duplicated effort, wasted resources, large inertia to change, and much user frustration as each different test format needs to be understood sufficiently to satisfy the demands of the consumer.
In response to this issue and specifically to address growing concerns with large volumes of digital test data, an industry consortium of IC producers and ATE manufacturers came together to develop a Standard Test Interface Language (STIL). STIL is designed to transfer high density digital test patterns between simulation, automatic test pattern generation (ATPG), built-in-self-test (BIST), and ATE.
The "Tools<>Tester" Consortium consisted of leaders in both the IC and ATE industries. It started with representation from: Lucent (formerly AT&T), IBM, Intel, Microchip, Motorola, NEC, TI, Advantest, Credence Systems, LTX, Schlumberger and Teradyne. As the effort has moved forward under the IEEE, participation has expanded.
Existing CAD tools have unique and differing software interfaces which are not portable into the unique ATE input interfaces. The definition of a standard language is beneficial to three parties:
With a standard between EDA, IC, and ATE environments, the generation, movement and processing of test data is greatly facilitated. This facilitation addresses a key issue with the handling of large digital test programs by defining a common format to contain this data.
A standard also allows for immediate access to test equipment supporting this standard. It benefits both ATE equipment manufacturers and IC vendors, removing the need for internal test interfaces supporting proprietary languages, and eliminating the inertia present when these interfaces need to be modified to support different equipment.
Finally, a cohesive standard allows for the creation of shared toolkits, generation environments, and identification of commonality in the test flow between vendors and in the test environment overall. Ultimately, this will benefit the IC designer as vendor-specific flows are replaced with common tool sets, and designers can operate on common data rather than data formatted for specific vendors.
The first effort at defining a focused standard for IC digital vector test representation, under the IEEE process, has resulted in IEEE Std 1450.0-1999. This is the definition of STIL.
STIL supports a tester-neutral description of timing, specifications, patterns and serial scan that can be generated by simulation conversion and ATPG tools. A powerful waveform representation supports the hierarchical definition of signal timing and is suitable for modern microprocessor bus structures. Timing may be defined as tables of timing specifications and timing relationships.
Test vector data may be defined using an incremental format, eliminating redundant data. Recurring vectors may be defined as procedure or macro information to further reduce the size of test data. STIL format is also structured in a manner that allows for incremental pattern file modification and reuse required by microprocessor vendors.
STIL stores serial scan data supporting full, partial or boundary scan in a format structured for direct test execution without requiring intervening test transformations.
The effort at standardizing additional aspects of IC digital test is underway. Based on interest in the Working Group, the standardization effort has been expanded with the definition of 5 (to date) "dotted extension" PARs. The current efforts are in the areas of:
Each of these efforts is a complete aspect of additional capability meant to be associated with the primary standard, 1450.0. They may be used individually or as a complete collection if the capability of each is necessary in a complete environment. Ultimately, it is expected that the 1450 series of standards will incorporate all of these efforts as a single package.
More information about these efforts can be found on the Overview for NESCOM document.
Other Cooperative Projects
The IEEE P1500 project is developing standards in support of embedded cores. The work being done by the language sub-committee of the P1500 is basing the "core test description language" on the STIL language. More information on the P1500 effort can be found on the P1500 web site.
The STIL Working Group (all activities) uses an IEEE-based email reflector to discuss the development process. The Working Group reflector is found at: email@example.com. Membership on this reflector is open to all. Subscribe (and unsubscribe) at: firstname.lastname@example.org. To subscribe, send an email to this address and state in the body of the email, on one line, subscribe stds-1450. To unsubscribe, state: unsubscribe stds-1450.
You may also contact the chairs of this effort directly:
|Tony Taylor||Greg Maston|