Phone Conference P1450.3 Working Group
Thursday, Sep 1, 2005 - 10:00-10:30 Pacific Time
Tony Taylor (chair & scribe)
- Dan's TRC document on the D4032 tester
- Bruce's email on missing parens
- moving tester TRC examples out of the document
- MaxVectorsCount statement
- Is TRC for a tester an instance or a class
IEEE meeting clearances
Nothing under discussion or presentation for this meeting was identified as being proprietary or restricted.
However, see discussion below about tester TRC files.
TRC file for Teseda tester
Bruce reports that he is pretty much complete with the TRC file and will send it to the wg for review at the next meeting.
Is TRC for a tester an instance or a class
We all agreed that a TRC block should be for a specific instance of a tester. Experience is showing that all possible configurations of a class of testers is too complex to put into one block. However, a TRC still needs to handle "fluid" or "soft" capabilities that can be supported in a given tester configuration - i.e., muxing to trade off speed vs. pin count.
ATE companies should consider a tool/script that allows to create a TRC block that represents a specific tester. This tool/script should allow for field modification that may be possible by a user.
STIL meetings at ITC
We discussed that Monday (i.e., during the pre-conf tutorials) would be the best time to have the dot3 and dot4 meetings. Tony will coordinate with Dave (and Jean-Louis) about this and will look into reserving a room.
We did not review specific syntax, however, two interesting suggestions arose from the discussion:
1. The "Inline|Once" definition is already covered by the MaxNest statement. i.e., if "MaxNest 0;" then it is necessary to inline everything.
2. The "MaxVectorsCount Vector" needs to handle both the case where one vector-memory generates multiple dut-vectors and where one dut-vector requires multiple vector-memory.
Tony will propose some syntax changes to handle this.
moving tester TRC examples out of the document
We all agreed that TRC files for specific ATE systems should not be placed in the standard. It is doubtful that we would get it exactly right and therefore need to be able to update them as needed. It may also be problematic to get clearance from the vendors to publish such detail in a standard (note: we would require a release from each company).
The thinking, at this time, is to use the www.stilusers.org public website to publish them.
Bruce's email on missing parens
Tony to fix this in the document.
Date: Next meeting Thursday, Sep
Time: 10:00 to 11:30 Pacific
AI-1: Bruce - create TRC for the Teseda tester using the D10
AI-2: Tony - coordinate with Dave to set up an ITC meeting - dot3 and dot4
AI-3: Tony - propose syntax for
MaxVectorCount (see above)