Your Name           _______________________________________________

Contact Information _______________________________________________

                    _______________________________________________

                    _______________________________________________

E-Mail Address      _______________________________________________

Specification ____ Design & Validation ____ DFT ____ Floorplanning ____ ATPG ____ Place & Route ____ Manufacture ____ Test ____ Failure Analysis ___

COMPONENT DEVELOPMENT

The principle core function(s) is (e.g., PCI, ATM, microprocessor, MPEGII)
________________________________________________________
Is reuse an objective for development of this core? Y___ N ___
Is core manufacture limited to your process technology? (HDL) NA ___ Y___ N ___
Is the core derived from a standalone IC? Y___ N ___


PORTABILITY OBJECTIVES

Do you plan internal (in-house) reuse for the core? Y___ N ___
Do you plan sale of this core to an external customer? Y___ N ___
Are existing ATPG Patterns to be reused with this core? Y___ N ___
Are Gate/Layout level descriptions to be provided to users? Y___ N ___
Are full timing simulation model(s) to be provided to users?
RTL level Y___ N ___
Gate-level Y___ N ___
Are interface/protocol simulation model(s) to be provided to users? Y___ N ___
Are timing shell(s) to be provided to users? Y___ N ___
For simulation Y___ N ___
For synthesis Y___ N ___

INTERNAL CORE LOGIC TYPES

Does the core contain:
Synchronous fully-static digital logic? Y___ N ___
Synchronous dynamic digital logic (e.g., domino)? Y___ N ___
Asynchronous (no clock) digital logic? Y___ N ___
Analog (e.g., PLL) circuits? Y___ N ___
Embedded static memory? Y___ N ___
Embedded dynamic memory? Y___ N ___
Internal Clock generation? Y___ N ___
Can ATE clock(s) override core internal clocks? Y___ N ___

CORE INTERNAL DFT

Are modifications made to enhance testability? Y___ N ___
Scan Method: Partial Scan ____ Full-scan ____
Scan Style: MUXed FF ____ Clocked Scan ____ LSSD ____ Other ____
Is RAM/ROMBIST used? Y___ N ___
Serial ____ Parallel ____
Is other Regular Structure BIST used? Y___ N ___
Is function-dependent BIST used? Y___ N ___
Is Logic/ScanBIST used? Y___ N ___
Is an IDDQ Testable State available? Y___ N ___
Any Other (Please Specify) ______________________________________________

CORE BOUNDARY
Specify the number of signal IO on the core boundary
Input #____ Outputs #____ Bi-directional #____
How is the direction of bi-directional core IO controlled? NA ____

____________________________________________________________


(e.g., Core Pins, JTAG controller, Other internal registers)

Can the core be in Hi-Z state, all outputs tri-stated? Y___ N ___
If yes, this state can be established by

____________________________________________________________

Can the core can be in safe state, where it cannot be harmed by changes on its input pins? Y___ N___
If yes, this state can be established by

____________________________________________________________

CORE BOUNDARY DFT

Is core boundary Scan or register bounding used? Y___ N ___
If yes, are boundary registers in
Series? ____ Parallel? ____ Both? ____
Is the core an 1149.1 "compatible" system by itself? Y___ N ___
Is a core bypass or transparency mode available? Y___ N ___
Are there other electrical concerns (internal SSO, noise, power, ...) for core testing?
____________________________________________________________

CORE TEST PATTERN CONTEXT

In what context(s) were test patterns generated? These context(s) or TEST MODES will need to be re-established with the embedded core to allow for reuse of the same patterns.

What kind of patterns are to be reused? ___________________________________________
What is their Test Vector Format? _________________________________________________
What is the simulation Vector Format (for signoff of test vectors)? ________________________
Are Static Timing analysis checks run for the Test modes? Y___ N ___

2. OVERALL IC TEST REQUIREMENTS

IC BOUNDARY

How many and what type of signal IO are on the IC boundary?

Input #____ Output #____ Bi-directional #____

How is the direction of bi-directional chip IO controlled? (0 bidis) NA ____

____________________________________________________________


(e.g., Core Pins, JTAG controller, Other internal registers)

Can the IC be in Hi-Z state, all outputs tri-stated? Y___ N ___
If yes, this state can be established by

____________________________________________________________

Is the IC 1149.1 compatible? Y___ N ___
How many pins can be dedicated to IC test (in addition to 1149.1)? # ____
Is diagnosis to the failing core required? Y___ N ___
Is diagnosis internal to each core required? Y___ N ___
Is parallel (concurrent) testing of cores required? Y___ N ___
Please provide a high Level description of testing of logic external to the core(s)
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

AC OR AT-SPEED TEST AND CHARACTERIZATION

Do you plan to test or characterize your core at-speed? (if no skip rest of this) Y___ N ___
How many clock domains does the core contain? # _____
If more than 1, are the domains synchronized with one another? Y___ N ___
What frequencies are used?
<50MHz _____ 50-100 MHz ______ 100-200 MHz ______ >200 MHz ______


Does your core have pins besides clock pins with special timing requirements? (e.g. signals which have timing requirements which do not correspond to a clock edge)
If so, do these requirements relate to (check all that apply)
chip pins_____
other cores_____
other logic in the chip_____

How many core I/O's are registered?
All ________ Most ________ Some ________ None ________

Do you plan to use functional test vectors
for test ________
for characterization ________
for both ________

Do you plan to use at-speed scan-based test vectors
for test ________
for characterization ________
for both ________


3. TEST ARCHITECTURE