Minutes of the IEEE P1500 Working Group Meeting
Montreal, May 5, 2000

Attendees

Debashis Bhattacharya  TI
Sudipta BhawmikLucent
Chen-Huan ChiangLucent
C.J. ClarkIntellitech
Mike CollinsCollins Design
Scott DavidsonSun
Bulent DervisogluIntellitech
Ted EatonSun
Alan HalesTI
Rohit KapurSynopsys
Douglas KayCisco
Brion KellerIBM
Adam LeyAsset Intertech
Monica Lobetti-BodoniSiemens
Maurice Lousberg  Philips
Samy MakarTransmeta
Erik Jan MarinissenPhilips
Teresa McLaurinMotorola
Fidel MuradaliAgilent
Stuart NelsonTeradyne
Rubin ParekhjiTI
Mike RicchettiIntellitech
Yiorgos TsiatouhasISD SA
Jon UdellPalmchip
Theodore VaidaLSI
Lee WhetselTI
Yervant ZorianLogicVision

Agenda

  1. Introduction and IEEE P1500 WG Update
    Y. Zorian, LogicVision
  2. Scalable Architecture Task Force Report
    L. Whetsel, Texas Instruments
    1. Instruction Tiger Team Report
      T. McLaurin, Motorola
    2. Wrapper Boundary Register Tiger Team Report
      J. Doege, Synopsys (presented by L. Whetsel, Texas Instruments)
    3. Wrapper Instruction Register Tiger Team Report
      Wrapper Instruction Register Specification
      M. Ricchetti, Intellitech
  3. Core Test Language Task Force Report
    R. Kapur, Synopsys
  4. Mergeable Cores Task Force Report
    S. Bhawmik, Lucent Technologies
    Mergeable Core Memory Test
    S. Davidson, Sun Microsystems
  5. Linking Task Force Report
    E.J. Marinissen, Philips
  6. Documentation Task Force Report
    E.J. Marinissen, Philips
  7. Discussion
    All

2. Scalable Architecture Task Force Report

Lee Whetsel presented an update on the P1500 scalable architecture task force work.

Q.
Is there any restriction on the wrapper cells?
A.
The behavior of the wrapper cells are defined by the standard. Not the implementation.

2a. Instruction Tiger Team Report

Teresa McLaurin presented the Wrapper Instruction tiger team update.

2b. Wrapper Boundary Register Tiger Team Report

Lee Whetsel presented the Wrapper Boundary register (WBR) tiger team update.

Q.
Are the updates done by holding the clock?
A.
Right now we have avoided the timing issues.

2c. Wrapper Instruction Register Tiger Team Report

Mike Ricchetti presented the WIR tiger team update.

Q.
How will this (examples etc) be described in the final standard? As rules?
A.
Examples will be in the information section of of the standards doc.

Q.
Why not represent the rules in some language like VHDL or Verilog?
A.
To retain the flexibility it is better to represent them in English. Also the group should not decide on how to implement the rules.

YZ:
Will check with IEEE if it allows to describe the rules in VHDL or Verilog.

Comment:
I have strong opposition to specifying a specific implementation. No linkage between WIR and other registers are desirable. State what you want to do, do not bother about how the rest of the structure should be. If the rule cannot be tested or verified from external ports, this should not be included in the rule set.

Q.
Does CTL have the capability of describing the WIR functions?
A.
CTL has a place holder for WIR.

Q.
Is there any place in the standard where the three, shift, update and capture order is specified?

Lee.
We will take these comments back and discuss and re-word if necessary.

Comment:
The name WIR is not appropriate since WIR also controls core test as well. Instruction register should be mandatory with the "1500 Ready" core too.

3. Core Test Language Task Force Report

Due to logistic issues, Mike Ricchetti's presentation was interrupted to allow Rohit Kapur to present the CTL task force update.

Q.
Is the parent child a container relationship or does the child borrow the properties of the parent?
A.
It is one of a borrowing concept.

Q.
Is this an inheritance property?
A:
Some characteristics are inherited, events are sequenced.

Q.
Is the example of extest same as Theresa's extest?
A.
Today CTL cannot specify that. We need to converge.

Q.
Can a signal have more than one data type?
A.
Yes.

Q.
Does there exist a keyword signifying that the core has a P1500 wrapper?
A:
There is a keyword "Wrapper" to specify whether it is wrapped or not. Not specifically P1500.

Q:
How are the IO ports mapped?
A:
It is taken care by STIL and they have a keyword.

Q:
Is it necessary to do 6 months of testing?
A:
It is necessary to do tests on 3/4 designs.

Comment:
Maybe it is better if other members (not in CTL TF) can do the testing by reading the doc.
Comment:
We'd like to have more examples from the CTAG or the other tiger teams.

Q:
Is there a CTL parser available to verify the CTL programs?
A:
STIL parsers should be able to handle CTL.

Q:
Is the interaction time with CTAG included?
A:
No. That should be a responsibility of the linking task force.

Q:
Are test patterns included in CTL?
A:
Yes.

Q:
Will there be a standard macro/include for P1500 wrapper specifics?
A:
Need to work on it. Language does not have to be upgraded to do that.

2c. Wrapper Instruction Register Tiger Team Report (continued)

Mike Ricchetti returned to present the remaining part of his WIR tiger team presentation.

Q:
Is WIP a collection of signals or logic?
A:
A collection of signal ports.

Comment:
The statement "Designed to have synchronous WIP ..." is confusing to people and may imply that WIP is some function.

Q:
Is this set of signals supposed to be present in the actual implementation?
A:
Yes.

Comment:
This forces an implementation.
Comment:
The wrapper and the WIR clocks may be separated, but has not been decided yet.

Q.
Are these signals generated from the control block.
A.
They could be.

Q.
Why is the WRSTN asynch? It can cause problems for ATPG.
A.
The rule should say, reset to normal mode. Asynch works better for any TRST.

Q.
Can level sensitive scan clocks be handled?
A.
The rules do not explicitly say that. Needs to be worked on.

Comment:
If 1149.1 type of LSSD support be provided, then how the scan operation works must also be specified. It seems that people would like to have a single edge triggered clock at the wrapper interface. For single edge triggered clock define what should happen at the rising and falling edges.

Mike Ricchetti proposed the following motion.

The motion was seconded by Scott Davidson.

Comment:
Should the rule include provisions for both single phase and dual phase clocks?

Lee Whetsel proposed the following friendly amended motion.

Comment:
For synthesizable RTL core, this may cause problems for negative edge triggered flop synthesis.

Voting on the motion:
For: 8 (7 valid votes)
Against: 6
Abstain: 0
The motion passed 8 to 6, but this was later revised to 7 to 6 because one of the "For" voters did not have P1500 voting rights.

4. Mergeable Cores Task Force Report

Sudipta Bhawmik presented an update on the Mergeable core test task force work. Scott Davidson spoke about the details of embedded memory test requirements.

Comment:
Multiple P1500 compliant cores can be potentially merged (after removing the wrapper). Such cases need to be considered. The CTL must be able to carry the information about the bare core and then wrap it. If a mergeable hard core (with all the information) is to be used, how can that be handled?

5. Linking Task Force Report

Erik Jan Marinissen presented an update on the Linking task force status.

In order to have appropriate names for the two levels of compliancy, the following motion was proposed and seconded.

Voting:
For the motion: 11 (Brian, Sudipta, Maurice, John, Mike, CJ, MikeC, Erik Jan, Scott, Alan, Doug)
Against: 0
Abstain: 2 (Fidel, Chen-Huan)

The motion passed 11 to 0.

6. Documentation Task Force Report

Erik Jan presented an update on the Documentation task force status.

Comment:
If a comment is sent which is not related to typo or format, it will be forwarded to the appropriate task force.

Q:
Why was CTL section put ahead of hardware architecture?
A:
CTL is required for unwrapped cores too. Hence give CTL to the readers first.

7. Discussion

It was decided that an informational meeting will be held during DAC on June 7th. It will be followed by a two day meeting.

The meeting was adjourned.