Minutes of IEEE P1500 Working Group Meeting
Los Angeles, CA
June 7th, 2000

Attendees

Sudipta Bhawmik  Lucent
Dwayne BurekLogicvision
Chen Huan ChiangLucent
Alan HalesTI
Rohit KapurSynopsys
Erik Jan MarinissenPhilips
Stuart NelsonTeradyne
Date Noorlag  MIPS
Lior PelogMysticom
Ian PhilipsARM
Justin PrayoguMysticom
Mike RicchettiIntellitech
Ted VaidaLSI
Yervant ZorianLogicvision

Minutes

  1. Yervant introduced the goals and objectives of P1500 and presented the agenda.

  2. Mike Ricchetti presented the update on CTAG task force work.

    Q:
    Why do you have mandatory, optional and user defined?
    A:
    To be consistent, such that optional instructions are not renamed.

    Q:
    Can WIR be loaded in parallel (broadside)?
    A:
    Yes. Intent is to capture internal responses.

    Q:
    Can we select an individual WIR and bypass others (while loading instructions)?
    A:
    It will depend on how SELECT WIR is connected. More details need to be worked out.

  3. Rohit Kapur presented an update on CTL with an emphasis on how to write a CTL for a core.

    Q:
    Can CTL for a core be elevated up to the system level through the TAM?
    A:
    Yes. One should be able to do that with minimum effort.

    Q:
    Can output property be floating?
    A:
    This issue may not be covered.

    Q:
    Can analog test be supported by CTL?
    A:
    We have not thought about it. It is a limitation now.

    Q:
    Are you testing CTL on real designs?
    A:
    Yes, we are manually testing CTL on real designs.

    Q:
    Is there a CTL parser available?
    A:
    Many companies are working on one. It should be do-able with few modifications to STIL parser.

  4. Ian Phillips presented ARM's experience on core test and emphasized the "need for functional testing in true SoC".

    Comments: P1500 wrapper is a common denominator test standard. It may be used for other purposes without violating the standard. Silicon debug is one of the issues. CTAG can consider debug access by creating an optional instruction. The CTAG team will consider this issue.

    Q: To what extent does this involve TAM? If it begins to look like TAM then we may not want to touch that.

    Comment: There should be a mode in which the boundary register as well as the internal scan chains can be used for debug purpose.

    How can we relate this to the NEXUS standard?

  5. Ted Vaida presented "LSI Logic's Core Test Issues"

  6. The meeting was adjourned.