Minutes of IEEE P1500 WG meeting
Dallas TX
Aug 28 & 29, 2000

Attendees

Minutes

1. Rohit Kapur presented an update on CTL task force from the last CTL-CTAG meeting. Actions taken (by the CTL task force) on the following items were:
   • Foreign construct : accepted
   • Foreign from other standard : modified accepted
   • Identifying tri-state outputs : accepted
   • File reference to internal CTL files : accepted
   • Rename capture clock and launch clock : rejected
     Q: Why is this needed?
     A: To inform the integrator how the clocks should b e activated in order to capture the data or launch data at the boundary.
   • CTL hierarchy to encapsulate modes : rejected
   • Upgrade ConnectTo : accepted
     ConnectTo applies to connecting terminals of a core to outside the core.
     ConnectTo Instruction - connect to an instruction register
     Comment: Use Test_Mode_Inputs instead of Instruction.
   • Macro Purpose add Reset Seq : rejected
   • Define multiple voltage levels : added (this is STIL dependent)

   Why are sample and preload separate instructions?
   In 1149.1 they have been separated.

   Diagnostics issue was not discussed within the TF. Wish to discuss on this later.

2. Jason Doege presented update on Wrapper boundary register (WBR) tiger team update

   Comments:

   • The semantics of the bubble diagram has to be completely defined
   • We can use some standard diagramming language where the semantics are defined
   • Can truth tables be defined?
     Truth tables are too detailed and specific. Bubble diagrams are not
   • Inward Facing (IF) mode mandatory or optional?
     restrictive.
   • The WBR described this way is too relaxed and may not offer plug and play.
   • If enough information is provided then automated tools can insert WBR and offer plug and play.
   • Lee: This is a proposal from Jason. CTAG has not yet approved of this open interface.

     If the reason for this is to allow legacy cores, then perhaps it should be mandatory.
     Prime focus is Intest, secondary is Extest.

   • All non-clock and non-dedicated test digital core terminals shall be provisioned in the WBR.

   Motion: We accept Rule 1 under IF rule as currently written in WBR tiger team notes:

   Rule 1: While in Inward Facing (IF) mode, cells provided for core inputs shall respond to Shift, Apply and if provisioned for it under WBR cell structure permission 5 above, Update events.

   Voted for the motion: 12
   Voted against the motion: 1
   Abstained: 2
   The motion passed.

   Rohit Kapur wrote a sample CTL for WBR

   Env { IEEE 1500
         CTL WEXTEST {
           TestMode Normal;
         }
   
         CTL myIntest {
           TestMode InternalTest;
           Internal {
             a { IsConnected In ScanChain c1; }
           }
   
           PatternInfo {
             Macro putgetval {
               Purpose Observe;
             }
   
             Macro putgetval {
               ScanChain name chain;
               V{ clk= ......}
               Shift{..........}
             }
   

   Action Item: Rohit will write a CTL for picoJava core. The Synthesized netlist will be provided by Rochit Rajsuman.

   Q: Can we have aliases (like #defines) in CTL?
   A: Yes. There is an example in the ITC99 paper that aliases the scanIn for the different configurations.

   Q: What is the use of test mode ExternalTest?
   A: For cores which do not have P1500 type external test modes.

   Since no cells can be both capture and update we must have instruction to support both Internaltest and Extest.
   By allowing multiple modes capability we can do that.

   Single wrapper cell can be shared between two cores. How does CTL handle this issue?
   Can be defined as two internal test modes.

   Update, Shift and Transfer can occur simultaneously. How can we define that?

3. Jon Udell presented his proposal on Unwrapping cores.

   Comments:

   Two sets of CTL can be kept for unwrapped and the wrapped cores. However if "undoing" of CTL is required it will be too difficult. Reword to take "unwrapping" out of this proposal.

4. Mike Richetti presented an update on the Wrapper Interface Port (WIP), WIR and Wrapper Bypass register.

   Q: What is the difference with 1149.1?
   A: 1149.1 TAP state machine is too restrictive. People can plug in TAP to WIP.

   Change the diagram to add the MUX to mux DR_WSO and WIR_WSO (in slide WIR Interface to bypass, WBR and CORE)

   CaptureWR signal can be optional for WIR.

   Q: How do you do WBR transfer?
   A: Not resolved yet.

   Do you have a power on reset seq for WIR?
   No. There is an asynch reset.

   Did we decide WBYPASS be one bit only?
   A: yes, it was decided some time ago.

   For hierarchical core the bypass at the top level may have more than one bits. The hierarchical wrapped core issue has not been resolved.

   Rohit Kapur presented an example of representing WIR in CTL.

5. Teresa McLaurin presented an update on the Wrapper Instruction tiger team work.

6. Other issues:
   • Open WBR control
     • provider must say how to have WBR control from WIP
     • Does this mean that system level integration will have to control the WBR for a system level controller?
     • If a provider provided a wrapped core with a controller outside WIP, they will have to provide detailed design info on how to control the WIP.