No progress on memory testing, but working on cleaning documents
STIL does not support memory algorithms
Currently, CTL group are checking definitions/syntax/keywords
3. CTAG Update by Lee
Wrapper serial interface layer
Architecture defined
Clocking scheme
Timing
Plug and play
TAP can operate WARTS interface
Wrapper parallel interface layer
Interface to wrapper TAM
Prepare documents
4. Documentation by Mike
(question by Rochit) PDF and hardcopy given to public is violating IEEE
rules!
(question by Maurice) when the other parts will be written?
MS Word to Framemaker
(question by Rohit) How many reviewers? How many reviews? Reviewers tend to
get less interested when the number of reviews increase. Lee agrees.
Rohit: CTL introduction part is not readable and readers are encouraged to
refer to ITC paper.
Rohit suggests to change agenda to meeting between CTL and CTAG. However,
it was not agreed by most of the participants. Meeting between two task
forces will take place after status update.
Teresa on Section6:
Teresa will write CTLs to Rohit.
Rohit: these instructions do not have keywords in CTL
Lee: wants to converge between CTL and CTAG
Rohit: wants CTL and CTAG NOT to converge, e.g. safe state in CTL and CTAG
Mike on Sections 2,3,4 and 7
Design and operate sections are separated
Newer version will be released on D.04
Jason on Section5
Need to define terminologies
Two features
Mode: static conditions
Event
Maurice and Mike and Jason
Regarding Maurice's comments in the email
Suggests to take recommendation out on internal core test
Rohit on CTL
ECUT: embedded CUT
P.2-10 WC_0 ...... WC_7 will be changed to CTAG definitions