IEEE P1500 Working Group meeting
June 20, 2001
DAC, Las Vegas

1. Introduction

Yervant Zorian presented a brief overview of the P1500 activities. It was mentioned that this meeting was primarily for information sharing with the community regarding the latest activities of the different task forces. Yervant mentioned that a new task force has been formed. This task force has been chartered to define the compliancy criteria for P1500. The task force is chaired by Erik Jan Marinissen.

Q.
Why does the unwrapped core CTL not describe how to test?
A.
It should describe. If not CTL must be fixed.

Q.
Is unwrapped core mergeable or non-mergeable?
A.
At this point it is non-mergeable. The information model should say if the core is mergeable or non-mergeable.

Q.
Partially wrapped signals can cause intermediate use models, how to ensure compliancy?
A.
Special case terminals can only be not wrapped. All others need to be wrapped.

Q.
Cores coming with a non compliant wrapper but a compliant CTL. What category does this fall into?
A.
This situation needs to be defined by the compliancy task force?

Q.
What diagnostics issue is covered in compliance?
A.
P1500 does not mandate any diagnostics, but CTL needs to be able to describe it if the core has any.

2. Core Test Language Task Force Report

Rohit Kapur presented the update on the CTL task force activities. CTL (syntax and semantics) will belong to 1450 standard (STIL). However, the information model will belong to P1500. Bulent objected to this multiple standards for the same issue. Commitment between two standards is impossible. Bulent proposed to separate the language at the second revision of the 1500 standard.

Sudipta raised the issue that whether the unwrapped core compliancy needed at all? Since CTL now belongs to a different standard, why should a description (of test features) in CTL for an unwrapped core be a IEEE 1500 standard? The group decided to discuss the issue at a later meeting and also in the Compliancy task force.

Q:
Does the 1500 unwrapped core come with a SIL or WIR?
A:
No it does not. It is a bare core.

Q:
Will on chip ATE or BIST constraints be considered as well in CTL?
A:
Yes.

3. Mergeable Cores Task Force Report

Sudipta Bhawmik presented an update on the Mergeable Core Test task force. However, it still remains to be decided where will the DFT Disclosure Document be published.

4. Scalable Architecture Task Force Report

Mike Ricchetti presented an update on Scalable Architecture design

Q:
Can TAM-in/TAM-out be scan chains?
A:
Yes. Also can interface with BIST, test bus etc.

Q:
Why 2 shift states in cell with all events?
A:
Good for applying 2 pattern tests.

Q:
Do we wrap cores with internal scan chain on I/O?
A:
If safe state is required, Yes.

Q:
In hierarchical cores, is any order required for cores?
A:
No.

5. Discussion

The following issues were agreed upon: