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The plug and play chapter is new as is the example reference chapter. There are some thoughts about adding to the examples.
The partially-wrapped cores material is postponed, until the completion of its discussion by the Working Group.
Review forms have been generated from IEEE database.
1450.6 and 1500 drafts will go out together. The reviewers will have 6 weeks to provide their review forms.
(Architecture Philosophy?); The idea is that the standard is a specification for architecture. It has been crafted to be as flexible as possible. The business of dealing with partially wrapped or un-wrapped cores is an implementation detail that should be handled by EDA tools.
The alternative is (the realist philosophy??) that a lot of the business is concerned with unwrapped or partially wrapped cores. If the standard does not address these issues it is liable to be irrelevant.
The major concern was with partially wrapped cores.
Grady emailed a document about difficulties with CTL when trying to wrap partially wrapped cores. And Rohit replied with some thoughts. The issue was how to deal with the dangling signals that need to come from the wrapper elements that aren't there to the wrapper elements that are included by the core provider. It was necessary to clarify how CTL might handle this case and if the things that are in place now to do this.
Examples were sighted of partially wrapped cores from ARM that typically come with a wrapper and no WIR or bypass register. In addition, cores that may be wrapped for 1149.1 either partially or completely may be candidates to be integrated into P1500 wrappers. Several participants thought that differential and bi-directional signals would likely come with the wrapper cell pre-installed. And, there was considerable discussion of shared functions; that is, wrapper logic that is part of the functional logic.
Rohit expressed the desire to give it "A good hard day" and look at what happens. He is optimistic that CTL can have a way to describe the operation of the "dangling signals" such that this is doable with a modification of the CTL.
This created an action item and an add hoc group headed by Rohit Kapur that includes but is not limitied to:
They are expected to have several meetings to come up with a full proposal to the Working Group to be presented in mid July time frame.
It was agreed that the Working Group meets to cover the remaining review process. This is mainly to discuss the last chapter of the D0.7.
The previous identified four patent holding companies have been approached by Yervant to inform us if their patents are essential.
Partially wrapped core ad-hoc team to prepare a proposal for the Working Group. WG meeting will be held on July 22.
Reviewers of D0.7 will report back by the first week in August.
The Documentation Task Force will continue to incorporate any changes from the above activities to D0.8, which will be the document for publication.
Meeting adjourned at 12pm (PDT)