Wednesday, May 3, 2000
| REGISTRATION: 2:00pm - 6:00pm | |
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| WORKSHOP OPENING:
4:00pm - 4:15pm
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| SESSION 1:
4:15pm - 6:45pm
Current Practices in System-on-Chip Test Session Moderator: L. Whetsel, Texas Instruments | |
| 1.1 | Test Access Methodology for System-on-Chip Testing, T.J. Chakraborty, C-H. Chiang, Bell Labs, Lucent Technologies | |
| 1.2 | A Practical DFT Strategy for a System-on-Chip, N. H. Tan, Infineon Technologies | |
| 1.3 | Embedded Macro Test Support in IBM's Test Bench Tools, B. Keller, R. Kerr, B. Koenemann, D. Pruden, R. Walther, IBM | |
| 1.4 | A Novel Approach for Designing Hierarchical Test Access Controller for Embedded Core Designs in an SOC Environment, B. Dervisoglu, Intellitech, J. Swamy, Cadence | |
| 1.5 | Evaluating Different Approaches for Embedded and External Testing, Monica Lobetti-Bodoni, Siemens Information and Communication Networks, Alfredo Benso, Stefano Di Carlo, Politecnico di Torino | |
| Discussion Panel:
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| RECEPTION: 6:45pm - 8:00pm | |
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| PANEL SESSION:
8:00pm - 9:30pm
The Role for Academic Research in SOC Test Co-Organized with: IEEE Design & Test of Computers Moderator: M. Chandramouli, Synopsys Organizer: Erik Jan Marinissen, Philips Panelists:
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Thursday, May 4, 2000
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| CONTINENTAL BREAKFAST: 7:00am - 8:00am | |
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| SESSION 2:
8:00am - 10:00am
New Approaches in Testing Embedded Cores Session Moderator: C. Papachristou, Case Western Univ | |
| 2.1 | On Design-for-Testability for Circuits Comprised of Non-Isolated Legacy Cores, I. Pomeranz, University of Iowa, Y. Zorian, LogicVision | |
| 2.2 | On Using Golomb Codes and Internal Scan Chains for Test Data Compression / Decompression in a System-on-a-Chip, A. Chandra, K. Chakrabarty, Duke University | |
| 2.3 | Test Information for Cores: Comparative Analysis and Recommendations, M.D. Quasem, S. Gupta, University of Southern California | |
| 2.4 | Controllable LFSR for Embedded Core BIST, D. Kay, Cisco Systems, S. Mourad, Santa Clara University | |
| Discussion Panel: Training IP Creators and
Integrators
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| COFFEE BREAK: 10:00am - 10:30am | |
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| SESSION 3:
10:30am - 12:30pm
Experiences in Testing Reusable Core-based Systems Session Moderator: T.W. Williams, Synopsys | |
| 3.1 | On-The-Shelf Core Pattern Methodology for Coldfire Cores, T.L. McLaurin, J.C. Potter, Motorola | |
| 3.2 | Testing Embedded Synthesizable IP - A Case Study, A. Burdass, G. Campbell, R. Grisenthwaite, R. York, G. Campbell, ARM | |
| 3.3 | HD2BIST: a Hierarchical Framework for BIST Scheduling, Data Patterns Delivering and Diagnosis in SOCs, A. Benso, D. DiCarlo, S. Chiusano, P. Prinetto, Poticecnico di Torino, M. Spadari, LSI Logic, Y. Zorian, LogicVision | |
| 3.4 | Test Methodology Framework for Embedded Core Based Systems, J. Abraham, N. Prasad, S. Chakravarthi, A. Bagwe, R. Parekhji, Texas Instruments | |
| Discussion Panel:
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| LUNCH: 12:30pm - 2:00pm | |
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| SESSION 4:
2:00pm - 4:30pm
Advanced Solutions for SOC Test and Verification Session Moderator: T. Anderson, 0-in | |
| 4.1 | Application Specific DSP Functional Validation Methodology, A. Daolio, F. Di Giovanni, S. Gazzaniga, G. Martinelli, ST Microelectronics | |
| 4.2 | Designer-Level Verification Using RuleBase, F. Busaba, B. Banerjee, C. Krygowski, IBM | |
| 4.3 | Intellectual Property Protection Using Partially-Mergeable Cores, V. Iyengar, M. Sugihara, H. Date, K. Chakrabarty, Duke University | |
| 4.4 | Effective Deterministic Arithmetic BIST Architecture for Embedded Processor Cores, A. Paschalis, University of Athens, N. Kranitis, Demokritos, D. Gizopoulos, University of Piraeus, M. Psarakis, Demokritos, Y. Zorian, LogicVision | |
| 4.5 | Controlling the CAS-BUS TAM with IEEE 1149.1 TAP: A Solution for Systems on a Chip Testing, W. Maroufi, M. Benabdenbi, M. Marzouki, LIP6/ ASIM Laboratory | |
| Discussion Panel:
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