GENERAL CHAIR
Y. Zorian, LogicVision
INDUSTRIAL LIAISON
K. Wagner, PMC-Sierra
FINANCE
R. Chandramouli, Synopsys
PUBLICATION
S. Dey, UC San Diego
PANELS
E.J. Marinissen,
Philips
PUBLICITY
B. Courtois, TIMA
A. Hales, Texas Instruments
ARRANGEMENTS
R. Rajsuman, Advantest
PROGRAM COMMITTEE
(to include)
R. Aitken, Agilent
J. Alt, Infineon
T. Anderson, 0-in
H. Bederr, Motorola
S. Bhawmik, Agere
D. Burek, LogicVision
K. Chakrabarty, Duke Univ
C.J. Clark, Intellitech
S. Davidson, Sun
R. Garcia, Schlumberger
D. Gizopoulos, 4PLUS
R. Gupta, UC Irvine
P. Harrod, ARM
R. Kapur, Synopsys
B. Keller, IBM
I. Kim, Agere
B. Koenemann, IBM
M. Lobetti-Bodoni, Siemens-ICN
M. Lousberg, Philips
S. Makar, Transmeta
E.J. McCluskey, Stanford Univ
T. McLaurin, ARM
F. Muradali, Agilent
M. Nicolaidis, iRoC
A. Orailoglu, UC San Diego
I. Pomeranz, Univ of Iowa
P. Prinetto, Politecnico di Torino
M. Renovell, LIRMM
M. Ricchetti, Intellitech
G. Robinson, Credence
R. Roy, Mobilian
A. Shubat, VirageLogic
J. Segura, Univ of Illes Balears
P. Teixeira, INESC
J. Udell, PalmChip
P. Varma, Veritable
L. Whetsel, Texas Instruments
T.W. Williams, Synopsys
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Embedded cores,
or pre-designed Intellectual
Property (IP) blocks, are finding growing use in microelectronic system-chips.
The increase in design reuse that core-based systems make possible adds to
the complexity of testing complete system-chips and even portions of them.
TECS 2001 is the workshop that dedicates its program to the state-of-the-art
practices and emerging trends in testing embedded core-based
system-chips. It brings together core creators, integrators, manufacturers and
ATE suppliers while providing an informal forum for presenting and discussing
new developments in testing such systems. The topics of interest include, but
are not limited to, the following:
- Automatic Test Generation for Embedded Cores
- BIST for IPs and System-Chips
- Core-level Design-for-Testability
- Debug and diagnosis for IP Cores
- Fault Modeling and Simulation
- Standard Test Solutions and IEEE P1500
- Test Control Mechanisms for System-on-Chip
- Verification and Validation for IPs
- Wrappers and Test Access Mechanisms for Cores
To present at the Workshop, authors are invited to submit paper proposals.
The proposals may be extended abstracts (1000 words) or full papers. Each
submission should include: title, full name and affiliation of all authors, an
abstract of 50 words, and keywords. Also, identify a contact author and
include a complete correspondence address, phone number, fax number, and
E-mail address. Submit six copies of your paper proposals by mail or an
electronic version (Word or PDF) via E-mail. Proposals for panel discussions
are also invited. Submissions are due no later than
March 2, 2001.
Submit your proposal to:
Authors will be notified of the disposition of their papers by March 30, 2001.
Authors of accepted papers may submit an illustrated text by April 13th
for inclusion in the Digest of Papers, which will be provided to the attendees.
TECS 2001 is sponsored by the
IEEE Computer Society Test Technology Technical Council
(TTTC) and in cooperation with VSIA -
The Virtual Socket Interface Alliance.
It is produced in conjunction with the
IEEE VLSI Test Symposium.
IEEE TECS 2001
1474 Freeman Dr.
Amissville, VA 20106
Tel: +1-540-937-8280
Fax: +1-540-937-7848
Email: tttc@computer.org
On the WWW:
www.computer.org/tab/tttc/meetings/home.html
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