TECS'01 Final Program

Wednesday, May 2, 2001

REGISTRATION: 2:00pm - 6:00pm
WORKSHOP OPENING: 4:00pm - 4:10pm

Welcome Address - Y. Zorian, General Chair

SESSION 1: 4:10pm - 6:00pm
Current Practices in System-on-Chip Test
Session Moderator: E.J. McCluskey, Stanford Univ
1.1 Philips' Approach to Core-based System Chip Testing, Erik Jan Marinissen, Philips
1.2 Full Built-In Self-Test Solution for System-on-Chip, D. Appello, F. DiGiovanni, M. Dusini, A. Fudoli, D. Lequile, F. Polloni, ST Microlelectronics
1.3 OPMISR: Accelerated Scan with on-Product Signatures, C. Barnhart, B. Keller, B. Koenemann, R. Walther, IBM
1.4 Iterative Test Wrapper and Test Access Mechanism Co-Optimization, Vikram Iyengar and Krishnendu Chakrabarty, Duke Univ
Discussion Panel:

Monica Lobetti-Bodoni, Siemens ICN
Rochit Rajsuman, Advantest
C.J. Clark, Intellitech

RECEPTION: 6:00pm - 8:00pm
PANEL SESSION: 8:00pm - 9:30pm
Do Core Providers Deliver What Core Users Require?
Co-Organized with: IEEE Design & Test of Computers
Moderator: Tom Anderson, 0-In
Organizer: Erik Jan Marinissen, Philips Research
Panelists:

Rob Aitken, Agilent
Sudipta Bhawmik, Agere
Andy Halliday, TriMedia
Maurice Lousberg, Philips
Teresa McLaurin, ARM Inc.
Avetik Yessayan, Virage Logic

Thursday, May 3, 2001

CONTINENTAL BREAKFAST: 7:00am - 8:00am
SESSION 2: 8:00am - 10:00am
New Approaches in Testing Embedded Cores
Session Moderator: A. Ivanov, Univ of British Columbia
2.1 Multi-Mode Scan: Test-per-Clock BIST for IP Cores, Adit Singh, Auburn Univ, Michael Goessel, Univ Potsdam, Egor Sogomonyan, RAS, and Peter Muhmenthaler, Infineon
2.2 Aliasing-free Space and Time Compaction for Embedded Cores, Ozgur Sinanoglu and Alex Orailoglu, UC San Diego
2.3 Using a Scan Simulation Model of a Random-Logic Embedded Core to Facilitate Test Generation for the Surrounding Logic, Irith Pomeranz, Purdue Univ, Yervant Zorian, LogicVision
2.4 MET: An Embedded Processor for Test Controlling, Erika Cota, Lisane Brisolara, Luigi Carro, Altamiro Susin and Marcelo Lubaszewski, UFRGS
Discussion Panel:

B. Keller, IBM
Meryem Marzouki, LIP6
S. Makar, Transmeta

COFFEE BREAK: 10:00am - 10:30am
SESSION 3: 10:30am - 12:30pm
Standardization and Experiences in Testing Reusable Core-based Systems
Session Moderator: Gordon Robinson, Credence
3.1 P1500 - CTL - The Core Test Language, T. Taylor, R. Kapur, Synopsys, M. Lousberg, Philips, B. Keller, IBM, P. Reuter, Mentor Graphics, D. Kay, Cisco
3.2 Tapping into P1500 Domains, L. Whetsel, Texas Instruments, M. Ricchetti, Intellitech
3.3 TAM Architectures and Their Implication on Test Application Time, Sandeep Kumar Goel, Erik Jan Marinissen, Philips
Discussion Panel:

Dwayne Burek, LogicVision
Gunnar Carlsson, Ericsson
Dimitris Gizopoulos, Univ of Preaeus

LUNCH: 12:30pm - 2:00pm
SESSION 4: 2:00pm - 4:00pm
Advanced Solutions for SOC Manufacturing & Test
Session Moderator: Mouli Chandaramouli, Synopsys
Invited Talk Design SOCs for Manufacturability David Y. Lepejian, HPL
4.1 Reducing Test Data Volume for Cores Using Dynamic LFSR Reseeding, C.V. Krishna, A. Jas, N. Touba, Univ of Texas at Austin
4.2 On Using Statistical Codes for System-on-a-Chip Test Data Compression, Anshuman Chandra, K. Chakrabarty, Duke Univ
4.3 Microprocessor-based Test Structures for SOC, Sungbae Hwang, Jacob Abraham, Univ of Texas at Austin
Discussion Panel:

Alfredo Benso, Polito di Torino
Sankaran Menon, Intel
M. Ricchetti, Intellitech

	REGISTRATION: 2:00pm - 6:00pm
	WORKSHOP OPENING: 4:00pm - 4:10pm Welcome Address - Y. Zorian, General Chair
	SESSION 1: 4:10pm - 6:00pm Current Practices in System-on-Chip Test Session Moderator: E.J. McCluskey, Stanford Univ
	1.1	Philips' Approach to Core-based System Chip Testing, Erik Jan Marinissen, Philips
	1.2	Full Built-In Self-Test Solution for System-on-Chip, D. Appello, F. DiGiovanni, M. Dusini, A. Fudoli, D. Lequile, F. Polloni, ST Microlelectronics
	1.3	OPMISR: Accelerated Scan with on-Product Signatures, C. Barnhart, B. Keller, B. Koenemann, R. Walther, IBM
	1.4	Iterative Test Wrapper and Test Access Mechanism Co-Optimization, Vikram Iyengar and Krishnendu Chakrabarty, Duke Univ
	Discussion Panel: Monica Lobetti-Bodoni, Siemens ICN Rochit Rajsuman, Advantest C.J. Clark, Intellitech
	RECEPTION: 6:00pm - 8:00pm
	PANEL SESSION: 8:00pm - 9:30pm Do Core Providers Deliver What Core Users Require? Co-Organized with: IEEE Design & Test of Computers Moderator: Tom Anderson, 0-In Organizer: Erik Jan Marinissen, Philips Research Panelists: Rob Aitken, Agilent Sudipta Bhawmik, Agere Andy Halliday, TriMedia Maurice Lousberg, Philips Teresa McLaurin, ARM Inc. Avetik Yessayan, Virage Logic

	CONTINENTAL BREAKFAST: 7:00am - 8:00am
	SESSION 2: 8:00am - 10:00am New Approaches in Testing Embedded Cores Session Moderator: A. Ivanov, Univ of British Columbia
	2.1	Multi-Mode Scan: Test-per-Clock BIST for IP Cores, Adit Singh, Auburn Univ, Michael Goessel, Univ Potsdam, Egor Sogomonyan, RAS, and Peter Muhmenthaler, Infineon
	2.2	Aliasing-free Space and Time Compaction for Embedded Cores, Ozgur Sinanoglu and Alex Orailoglu, UC San Diego
	2.3	Using a Scan Simulation Model of a Random-Logic Embedded Core to Facilitate Test Generation for the Surrounding Logic, Irith Pomeranz, Purdue Univ, Yervant Zorian, LogicVision
	2.4	MET: An Embedded Processor for Test Controlling, Erika Cota, Lisane Brisolara, Luigi Carro, Altamiro Susin and Marcelo Lubaszewski, UFRGS
	Discussion Panel: B. Keller, IBM Meryem Marzouki, LIP6 S. Makar, Transmeta
	COFFEE BREAK: 10:00am - 10:30am
	SESSION 3: 10:30am - 12:30pm Standardization and Experiences in Testing Reusable Core-based Systems Session Moderator: Gordon Robinson, Credence
	3.1	P1500 - CTL - The Core Test Language, T. Taylor, R. Kapur, Synopsys, M. Lousberg, Philips, B. Keller, IBM, P. Reuter, Mentor Graphics, D. Kay, Cisco
	3.2	Tapping into P1500 Domains, L. Whetsel, Texas Instruments, M. Ricchetti, Intellitech
	3.3	TAM Architectures and Their Implication on Test Application Time, Sandeep Kumar Goel, Erik Jan Marinissen, Philips
	Discussion Panel: Dwayne Burek, LogicVision Gunnar Carlsson, Ericsson Dimitris Gizopoulos, Univ of Preaeus
	LUNCH: 12:30pm - 2:00pm
	SESSION 4: 2:00pm - 4:00pm Advanced Solutions for SOC Manufacturing & Test Session Moderator: Mouli Chandaramouli, Synopsys
	Invited Talk	Design SOCs for Manufacturability David Y. Lepejian, HPL
	4.1	Reducing Test Data Volume for Cores Using Dynamic LFSR Reseeding, C.V. Krishna, A. Jas, N. Touba, Univ of Texas at Austin
	4.2	On Using Statistical Codes for System-on-a-Chip Test Data Compression, Anshuman Chandra, K. Chakrabarty, Duke Univ
	4.3	Microprocessor-based Test Structures for SOC, Sungbae Hwang, Jacob Abraham, Univ of Texas at Austin
	Discussion Panel: Alfredo Benso, Polito di Torino Sankaran Menon, Intel M. Ricchetti, Intellitech