TECS'02 Final Program

Wednesday, May 1, 2002

REGISTRATION: 2:00pm - 5:00pm
WORKSHOP OPENING SESSION: 4:00pm - 4:45pm

Welcome Address - Y. Zorian, General Chair
Keynote Talk - "SoC Test: A Survey of Viewpoints", Ron Wilson, Editorial Director and Group Research Director, ISD Magazine & EE Times

SESSION 1: 4:45pm - 6:45pm
Current Practices in System-on-Chip Test
Session Moderator: M. Lousberg, Philips
1.1 Practical Applications and Use of Embedded Cores for Defect and Functional Testing, J. A. Raynick, eSilicon
1.2 A Test Access Control and Test Integration System for System-on-Chip, C-Wang, J-R Huang, K-L Cheng, H-S Hsu, C-T Huang, C-W Wu, National Tsing Hua Univeristy, and Y-L Lin, Global UniChip Corp.
1.3 X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction, S. Mitra, K. S. Kim, Intel
Discussion Panel:

L. Basto, Analog Devices
M. Chandaramouli, Synopsys
B. Keller, IBM
M. Ricchetti, Intellitech

RECEPTION: 7:00pm - 9:00pm

Thursday, May 2, 2002

CONTINENTAL BREAKFAST: 7:00am - 8:00am
SESSION 2: 8:00am - 10:00am
New Approaches in Testing Embedded Cores
Session Moderator: C.J. Clark, Intellitech
2.1 De-Coupling Test Data Communication and Control/Observation for Scan-based Testing in System-on-Chip, M. Nahvi, A. Ivanov, R. Saleh, University of British Columbia
2.2 IP for Embedded Diagnosis, S. Pateras, LogicVision
2.3 Built-In Self-Test, Redundancy Analysis and Self-Repair in the Context of Embedded DRAM, P. Sidorowicz, ATMOS Corp
2.4 The VSI Alliance Test Access Architecture Standard, Samy Makar, Transmeta, T. Ayres, Silicon Access, F. Bouwman, Philips, R. Chandramouli, Synopsys, B. Cordan, Palmchip, P. Fasang, Hitachi, R. Garcia, Schlumberger, S. Mukherji, Neomagic, P. Varma, Veritable
Discussion Panel:

T. McLaurin, ARM
F. Muradali, Agilent
A. Orailoglu, UC San Diego
T. Taylor, Synopsys

COFFEE BREAK: 10:00am - 10:30am
SESSION 3: 10:30am - 12:00pm
Panel Session: How Useful Are The ITC'02 SOC Test Benchmarks?
Co-Organized with: IEEE Design & Test of Computers
Organizer: Erik Jan Marinissen, Philips Research
Moderator: Krishnendu Chakrabarty, Duke University
Panelists: Dwayne Burek, LogicVision
Andre Ivanov, UBC
Brion Keller, IBM Microelectronics
Sandeep Koranne, Tanner Research
Erik Jan Marinissen, Philips Research
Paul Reuter, Mentor Graphics
LUNCH: 12:30pm - 2:00pm
SESSION 4: 2:00pm - 4:00pm
Advanced Solutions for SOC Manufacturing & Test
Session Moderator: J. Sproch, Synopsys
4.1 In-Context Functional Verification of Embedded Cores, Tom Anderson, 0-in
4.2 Test Hardware/Software Co-synthesis for Systems-on-a-Chip, N. Nicolici, McMaster University, Canada
4.3 On Approach for CTL Implementation, S. Baghdasaryan, State Engineering University, S. Shoukourian, Yerevan State University, Armenia
4.4 A Simple and Reusable Test Access Mechanism for SOC Validation, I.Z. Theologitou, F.E. Karoubalis, G.A. Doumenis, National Technical Univeristy of Athens, Greece
Discussion Panel:

J. Doege, Inovys
D. Gizopoulos, Univ of Piraeus
A. Hales, Texas Instruments
J. Segura, Univ of Illes Balears

	REGISTRATION: 2:00pm - 5:00pm
	WORKSHOP OPENING SESSION: 4:00pm - 4:45pm Welcome Address - Y. Zorian, General Chair Keynote Talk - "SoC Test: A Survey of Viewpoints", Ron Wilson, Editorial Director and Group Research Director, ISD Magazine & EE Times
	SESSION 1: 4:45pm - 6:45pm Current Practices in System-on-Chip Test Session Moderator: M. Lousberg, Philips
	1.1	Practical Applications and Use of Embedded Cores for Defect and Functional Testing, J. A. Raynick, eSilicon
	1.2	A Test Access Control and Test Integration System for System-on-Chip, C-Wang, J-R Huang, K-L Cheng, H-S Hsu, C-T Huang, C-W Wu, National Tsing Hua Univeristy, and Y-L Lin, Global UniChip Corp.
	1.3	X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction, S. Mitra, K. S. Kim, Intel
	Discussion Panel: L. Basto, Analog Devices M. Chandaramouli, Synopsys B. Keller, IBM M. Ricchetti, Intellitech
	RECEPTION: 7:00pm - 9:00pm

CONTINENTAL BREAKFAST: 7:00am - 8:00am
SESSION 2: 8:00am - 10:00am New Approaches in Testing Embedded Cores Session Moderator: C.J. Clark, Intellitech
2.1	De-Coupling Test Data Communication and Control/Observation for Scan-based Testing in System-on-Chip, M. Nahvi, A. Ivanov, R. Saleh, University of British Columbia
2.2	IP for Embedded Diagnosis, S. Pateras, LogicVision
2.3	Built-In Self-Test, Redundancy Analysis and Self-Repair in the Context of Embedded DRAM, P. Sidorowicz, ATMOS Corp
2.4	The VSI Alliance Test Access Architecture Standard, Samy Makar, Transmeta, T. Ayres, Silicon Access, F. Bouwman, Philips, R. Chandramouli, Synopsys, B. Cordan, Palmchip, P. Fasang, Hitachi, R. Garcia, Schlumberger, S. Mukherji, Neomagic, P. Varma, Veritable
Discussion Panel: T. McLaurin, ARM F. Muradali, Agilent A. Orailoglu, UC San Diego T. Taylor, Synopsys
COFFEE BREAK: 10:00am - 10:30am
SESSION 3: 10:30am - 12:00pm Panel Session: How Useful Are The ITC'02 SOC Test Benchmarks? Co-Organized with: IEEE Design & Test of Computers
Organizer:		Erik Jan Marinissen, Philips Research
Moderator:		Krishnendu Chakrabarty, Duke University
Panelists:		Dwayne Burek, LogicVision Andre Ivanov, UBC Brion Keller, IBM Microelectronics Sandeep Koranne, Tanner Research Erik Jan Marinissen, Philips Research Paul Reuter, Mentor Graphics
LUNCH: 12:30pm - 2:00pm
SESSION 4: 2:00pm - 4:00pm Advanced Solutions for SOC Manufacturing & Test Session Moderator: J. Sproch, Synopsys
4.1	In-Context Functional Verification of Embedded Cores, Tom Anderson, 0-in
4.2	Test Hardware/Software Co-synthesis for Systems-on-a-Chip, N. Nicolici, McMaster University, Canada
4.3	On Approach for CTL Implementation, S. Baghdasaryan, State Engineering University, S. Shoukourian, Yerevan State University, Armenia
4.4	A Simple and Reusable Test Access Mechanism for SOC Validation, I.Z. Theologitou, F.E. Karoubalis, G.A. Doumenis, National Technical Univeristy of Athens, Greece
Discussion Panel: J. Doege, Inovys D. Gizopoulos, Univ of Piraeus A. Hales, Texas Instruments J. Segura, Univ of Illes Balears