GENERAL CHAIR
Y. Zorian, LogicVision
FINANCE
R. Chandramouli, Synopsys
INDUSTRIAL LIAISON
K. Wagner, S3
ARRANGEMENTS
E.J. Marinissen,
Philips
REGISTRATION
R. Rajsuman, Advantest
PUBLICITY
B. Courtois, TIMA
A. Hales, Texas Instruments
PUBLICATION
S. Dey, NEC USA
PANELS
PROGRAM COMMITTEE
(to include)
R. Aitken, Hewlett-Packard
J. Alt, Siemens
T. Anderson, Phoenix
S. Barbagallo, Italtel
D. Bhavsar, DEC
D. Burek, LogicVision
G. Carlsson, Ericsson
S. Chung, Cisco
C.J. Clark, Intellitech
S. Davidson, Sun
T. Eberle, Mentor Graphics
R. Garcia, Schlumberger
G. Giles, Motorola
D. Gizopoulos,
NCSR Demokritos
R. Gupta, Univ of Cal Irvine
S. Hemmady, Guru Technologies
J.P. Hayes, Univ. of Michigan
I. Kim, Lucent Technologies
B. Koenemann, LogicVision
C. Mallipeddi, Cadence
E.J. McCluskey, Stanford Univ
J. Monzel, IBM
S. Mukherjee, Fujitsu
F. Muradali, Hewlett-Packard
M. Nicolaidis, TIMA
A. Orailoglu,
Univ Cal San Diego
C. Papachristou,
Case Western Reserve
I. Pomeranz, Univ of Iowa
P. Prinetto, Poli di Torino
J. Rajski, Mentor Graphics
M. Renovell, LIRMM
G. Robinson, Credence
R. Roy, Intel
R. Segers, Philips
M. Spadari, LSI Logic
E. de la Torre,
Univ. Poli Madrid
J. Udell, PalmChip
P. Varma, Duet Technologies
L. Whetsel, Texas Instruments
T. Williams, Synopsys
|
Embedded cores,
or pre-designed Intellectual
Property (IP) blocks, are finding growing use in microelectronic system-chips.
The increase in design reuse, that core-based systems make possible, adds to
the complexity of testing the complete system-chips and even portions of it.
TECS'98 is the workshop that dedicates its program to the state-of-the-art
practices and emerging trends of testing embedded core-based
system-chips. It brings together core creators, integrators and manufacturers
while providing an informal forum for presenting and discussing the new
developments in testing such systems. The topics of interest include, but
are not limited to, the following:
- Automatic Test Generation for System-Chips
- BIST for System-Chips
- Core-level BIST
- Debug and diagnosis for IP Cores
- Design-for-Testability for Embedded Cores
- Fault Modeling and Simulation
- Synthesis for Testability
- Test Control and Access for Embedded Cores
- Verification and Validation for embedded IPs
To present at the Workshop, authors are invited to submit paper proposals.
The proposals may be extended abstracts (1000 words) or full papers. Each
submission should include: title, full name and affiliation of all authors, an
abstract of 50 words, and keywords. Also, identify a contact author and
include a complete correspondence address, phone number, fax number, and
E-mail address. Submit 6 copies of your paper proposals by mail or Postscript
version via E-mail. Proposals for panel discussions are also invited.
Submissions are due no later than June 29nd, 1998.
Submit your paper proposal to:
Authors will be notified of the disposition of their papers by August 25th,
1998. Authors of accepted papers may submit an illustrated text September 25th
for inclusion in the Digest of Papers, which will be provided to the attendees.
A selected set of papers from TECS'98 will be considered for inclusion
in a forthcoming special issue on testing core-based system-chips.
TECS'98 is sponsored by the
IEEE Computer Society Test Technology Technical Committee
(TTTC) and in cooperation with VSIA -
The Virtual Socket Interface Alliance.
It is produced in conjunction with Test Week 98 and the
International Test Conference.
IEEE TECS
1474 Freeman Dr.
Amissville, VA 20106
Tel: +1-540-937-8280
Fax: +1-540-937-3739
Email: tttc@computer.org
On the WWW:
www.computer.org/tab/tttc/meetings/tecs/
|
