TECS'98 Final Program

Thursday, October 22

REGISTRATION: 2:00pm - 7:00pm
OPENING SESSION: 4:00pm - 5:00pm

Welcome Address - Y. Zorian, General Chair
Invited Presentation - The Market for System-on-Chip Testing, R. Puhakka, VLSI Research Inc.

SESSION 1: 5:00pm - 6:30pm
Current Practices in System-on-Chip Test
Session Moderator: Gordon Robinson, Credence Systems
1.1 Addressable Test Ports an Approach to Testing Embedded Cores, Lee Whetsel, Texas Instruments
1.2 IP/VC-based Test Methodology: A Case Study, Sobhan Mukherji*, Loc Nguyen, Fujitsu, Dwayne Burek, Steve Baird, Tosh Hirasawa, S. Aryani, LogicVision
1.3 An Industrial Approach to Core Testing, A. Benso, Politecnico di Torino, G. Borgonovo, D. Grassi, M. Lobetti Bodoni*, A. Pricco, Italtel, Italy
Discussion Panel:

Rob Aitken, HP
Mike Ricchetti, Synopsys
Shianling Wu, Lucent Technologies

RECEPTION: 7:00pm - 9:00pm

Friday, October 23

BREAKFAST: 7:00am - 8:00am
SESSION 2: 8:00am - 10:00am
New Approaches in Testing Embedded Cores
Session Moderator: P. Teixeira, INESC, Portugal
2.1 Issues in Testing of Non-Isolated Embedded Cores and their Surrounding Logic, Irith Pomeranz*, University of Iowa, Yervant Zorian, LogicVision
2.2 A Novel Approach to Optimizing IEEE 1149.1 for Systems with Multiple Embedded Cores, Jake Karrfalt, ASC, Zainalabedin Navabi*, Notheastern University, Casper Stoel, ASC
2.3 Incremental Test of Bus-Oriented Designs, Aziz Fortas*, Ronald Tangelder, Hans Kerkhoff, University of Twente, The Netherlands
2.4 HD-BIST: a Hierarchical Distributed BIST Architecture for SOC, Alfredo Benso*, Silvia Chiusano, Paolo Prinetto, Politecnico di Torino, Italy, Yervant Zorian, LogicVision
Discussion Panel:

Scott Davidson, Sun
Michael Nicolaidis, TIMA
Nur Touba, University of Texas

COFFEE BREAK: 10:00am - 10:30am
SESSION 3: 10:30am - 12:30pm
Experiences in Testing Reusable Core-based Systems
Session Moderator: E.J. McCluskey, Stanford University
3.1 SOC Test Issues for Interconnect Cores, Thomas L. Anderson, Phoenix Technologies
3.2 Test Strategy for TI's TMS320AV7100 Device, Jayashree Saxena*, Paul Policke, Ken Cyr, Agapito Benavides, Harry Malpass, Francis Ngoh, Texas Instruments
3.3 A Production Test Environment for Complex System on a Chip ASIC Products Incorporating the Rambus ASIC Cell, Kevin M. Grosselfinger*, James A.Monzel, IBM
3.4 A New Test Methodology for Testing Embedded Memories in Core-based System-on-a-Chip ICs, Rochit Rajsuman, Advantest
Discussion Panel:

Bill Bottoms, Credence Systems
Brion Keller, IBM
Jim Sproch, Synopsys

Coorganized with: IEEE Design & Test of Computers
LUNCH: 12:30pm - 1:30pm
SESSION 4: 1:30pm - 2:30pm
Invited Session
The Prospects of Test Standardization: IEEE P1500, Yervant Zorian, LogicVision, Lee Whetsel, Texas Instruments, Rohit Kapur, Synopsys
SESSION 5: 2:30pm - 4:00pm
Philips' Approach to Core Test
Session Moderator: Rene Segers, Philips
5.1 Core based Test for a System on Chip Architecture Framework, Robert Arendsen*, Maurice Lousberg, Philips Semiconductor, The Netherlands
5.2 Integration of Structural-test Methods into an Architecture Specific Core-Test Approach, Chris Feige*, Clemens Wouters, Philips Semiconductor, The Netherlands
5.3 Test Protocol Scheduling for Embedded-Core Based System ICs, Erik Jan Marinissen*, Joep Aerts, Philips Research Laboratories, The Netherlands
Discussion Panel:

Debashis Bhattacharya, Texas Instruments
Richard Chrusciel, Advantest
R. Chandramouli, Synopsys
Dimitris Gizopoulos, 4PLUS

	REGISTRATION: 2:00pm - 7:00pm
	OPENING SESSION: 4:00pm - 5:00pm Welcome Address - Y. Zorian, General Chair Invited Presentation - The Market for System-on-Chip Testing, R. Puhakka, VLSI Research Inc.
	SESSION 1: 5:00pm - 6:30pm Current Practices in System-on-Chip Test Session Moderator: Gordon Robinson, Credence Systems
	1.1	Addressable Test Ports an Approach to Testing Embedded Cores, Lee Whetsel, Texas Instruments
	1.2	IP/VC-based Test Methodology: A Case Study, Sobhan Mukherji*, Loc Nguyen, Fujitsu, Dwayne Burek, Steve Baird, Tosh Hirasawa, S. Aryani, LogicVision
	1.3	An Industrial Approach to Core Testing, A. Benso, Politecnico di Torino, G. Borgonovo, D. Grassi, M. Lobetti Bodoni*, A. Pricco, Italtel, Italy
	Discussion Panel: Rob Aitken, HP Mike Ricchetti, Synopsys Shianling Wu, Lucent Technologies
	RECEPTION: 7:00pm - 9:00pm

	BREAKFAST: 7:00am - 8:00am
	SESSION 2: 8:00am - 10:00am New Approaches in Testing Embedded Cores Session Moderator: P. Teixeira, INESC, Portugal
	2.1	Issues in Testing of Non-Isolated Embedded Cores and their Surrounding Logic, Irith Pomeranz*, University of Iowa, Yervant Zorian, LogicVision
	2.2	A Novel Approach to Optimizing IEEE 1149.1 for Systems with Multiple Embedded Cores, Jake Karrfalt, ASC, Zainalabedin Navabi*, Notheastern University, Casper Stoel, ASC
	2.3	Incremental Test of Bus-Oriented Designs, Aziz Fortas*, Ronald Tangelder, Hans Kerkhoff, University of Twente, The Netherlands
	2.4	HD-BIST: a Hierarchical Distributed BIST Architecture for SOC, Alfredo Benso*, Silvia Chiusano, Paolo Prinetto, Politecnico di Torino, Italy, Yervant Zorian, LogicVision
	Discussion Panel: Scott Davidson, Sun Michael Nicolaidis, TIMA Nur Touba, University of Texas
	COFFEE BREAK: 10:00am - 10:30am
	SESSION 3: 10:30am - 12:30pm Experiences in Testing Reusable Core-based Systems Session Moderator: E.J. McCluskey, Stanford University
	3.1	SOC Test Issues for Interconnect Cores, Thomas L. Anderson, Phoenix Technologies
	3.2	Test Strategy for TI's TMS320AV7100 Device, Jayashree Saxena*, Paul Policke, Ken Cyr, Agapito Benavides, Harry Malpass, Francis Ngoh, Texas Instruments
	3.3	A Production Test Environment for Complex System on a Chip ASIC Products Incorporating the Rambus ASIC Cell, Kevin M. Grosselfinger*, James A.Monzel, IBM
	3.4	A New Test Methodology for Testing Embedded Memories in Core-based System-on-a-Chip ICs, Rochit Rajsuman, Advantest
	Discussion Panel: Bill Bottoms, Credence Systems Brion Keller, IBM Jim Sproch, Synopsys Coorganized with: IEEE Design & Test of Computers
	LUNCH: 12:30pm - 1:30pm
	SESSION 4: 1:30pm - 2:30pm Invited Session
	The Prospects of Test Standardization: IEEE P1500, Yervant Zorian, LogicVision, Lee Whetsel, Texas Instruments, Rohit Kapur, Synopsys
	SESSION 5: 2:30pm - 4:00pm Philips' Approach to Core Test Session Moderator: Rene Segers, Philips
	5.1	Core based Test for a System on Chip Architecture Framework, Robert Arendsen*, Maurice Lousberg, Philips Semiconductor, The Netherlands
	5.2	Integration of Structural-test Methods into an Architecture Specific Core-Test Approach, Chris Feige*, Clemens Wouters, Philips Semiconductor, The Netherlands
	5.3	Test Protocol Scheduling for Embedded-Core Based System ICs, Erik Jan Marinissen*, Joep Aerts, Philips Research Laboratories, The Netherlands
	Discussion Panel: Debashis Bhattacharya, Texas Instruments Richard Chrusciel, Advantest R. Chandramouli, Synopsys Dimitris Gizopoulos, 4PLUS