PROGRAM at a GLANCE

Wednesday, April 28
2:00pm- 7:00pm Registration
4:00pm- 4:45pm Opening Session
4:45pm- 6:45pm Session 1: Current Practices in System-on-Chip Test
6:45pm- 8:00pm Evening Reception
8:00pm- 9:30pm Panel Session: CAD Tools for Core Test
Thursday, April 29
7:00am-8:00am Continental Breakfast
8:00am-10:00am Session 2: New Approaches in Testing Embedded Cores
10:00am-10:30amCoffee Break + Poster Session
10:30am-12:30pm Session 3: Experiences in Testing Embedded Core-based Systems
12:30pm-1:30pm Lunch
1:30pm-2:30pm Invited Session: The Prospects of Core Test: VSIA Manufacturing Test DWG
2:30pm-4:30pm Session 4: Advanced Solutions for SOC Testing

Paper Sessions: All four sessions at TECS'99 are comprised of paper presentations followed by dedicated discussion panels to conclude the sessions with recommendations and roadmaps.

Keynote: TECS'99 starts with a keynote address by Rene Segers, Philips Semiconductors, entitled: "Philips' Experiences in Core-based Design and Test of System ICs"

Panel Session: TECS'99 for the first time features a full length panel on "CAD Tools for Core Test". The panelists represent commercial EDA tool vendors, internal tool providers and users. This panel is co-organized with IEEE Design & Test of Computers.

IEEE P1500 (Embedded Core Test Standard): The P1500 Working Group will hold its periodic meeting in conjunction with TECS'99 immediately following the workshop. The P1500 Working Group meeting schedule is held in two parts:

No registration is required to attend the IEEE P1500 Working Group meeting.