TECS'99 Final Program

Wednesday, April 28, 1999

REGISTRATION: 2:00pm - 7:00pm
OPENING SESSION: 4:00pm - 4:45pm

Welcome Address - Y. Zorian, General Chair
Keynote Address - Philips' Experience in Core-Based Design and Test of System ICs, R. Segers, Philips Semiconductors

SESSION 1: 4:45pm - 6:45pm
Current Practices in System-on-Chip Test
Session Moderator: T.W. Williams, Synopsys
1.1 System-Level-Integration Test Hardware and its Impact on Reuse and Design, F. Muradali, R. Aitken, N. Jaarsma
1.2 Strategies for Testing Embedded Cores at Cirrus Logic, S. Makar, Cirrus Logic
1.3 At-Speed Test of a DSP Subsystem Embedded in a Wireless Application Chip, H. Bederr, F. Chirat, Texas Instruments, France
1.4 A Hierarchical Test Methodology involving Multiple Embedded Cores having Different DFT Mechanisms, M. Spadari, T. Vaida, P. Ghosh, LSI Logic
Discussion Panel:

R. Kapur, Synopsys
W. Ke, Cadence
M. Nicolaidis, TIMA
L. Whetsel, Texas Instruments

RECEPTION: 6:45pm - 8:00pm
PANEL SESSION: 8:00pm - 9:30pm
CAD Tools for Core Test
Co-Organized with: IEEE Design & Test of Computers
Moderator: Erik Jan Marinissen, Philips
Panelists:

Michael Howells, LogicVision
Teresa McLaurin, Motorola
Maurice Lousberg, Philips ED&T
Srinivas Patil, Mentor Graphics
Maurizio Spadari, LSI Logic

Thursday, April 29, 1999

CONTINENTAL BREAKFAST: 7:00am - 8:00am
SESSION 2: 8:00am - 10:00am
New Approaches in Testing Embedded Cores
Session Moderator: D. Bouldin, University of Tennessee
2.1 A Method for Path Delay Fault ATPG in Embedded Cores, S. Tragoudas, M. Michael, University of Arizona
2.2 On Testing of Non-Isolated Sequential Embedded Cores and their Surrounding Logic, I. Pomeranz, University of Iowa, Y. Zorian, LogicVision
2.3 Microprocessor Based Testing for Core-based System-on-Chip, F. Martin, C. Papachristou, Case Western Reserve University
Discussion Panel: Training IP Creators and Integrators

S. Dey, UCSD
D. Gizopoulos, 4Plus
M. Lobetti, Italtel
R. Rajsuman, Advantest

COFFEE BREAK and POSTER SESSION: 10:00am - 10:30am
Probabilistic IP Verification, R. Drechsler, B. Becker, Albert-Ludwigs-University, Germany
A Programmable BIST Compiler for Memory Cores, K-J. Lin, C-W Wu, National Tsing Hua University, Taiwan
Testability Verification of Embedded Systems based on Weak Mutation Analysis, F. Vargas, E. Bezerra, A. Terroso, PUCRS
SESSION 3: 10:30am - 12:30pm
Experiences in Testing Reusable Core-based Systems
Session Moderator: Rob Roy, Intel
3.1 Generating Core Test Control Mechanisms, G.E.A. Lousberg, Philips Research, The Netherlands
3.2 Design for Test in TI's TMS320C27xx: Techniques for Achieving High Fault Coverage in Embedded Cores, B.S.S. Chakravarthy, M.S. Rao, J. Abraham, R.A. Parekhji, Texas Instruments, India
3.3 The Embedded DRAM Test Dilemma, D. Richter, C. Hoffmann, V. Kilian, Siemens Semiconductors Group, Germany
3.4 A Virtual Test Approach for Reusable Core Test IP, E. Perkins, M.R. Jones, IMS
Discussion Panel:

R. Aitken, HP
D. Bhattacharya, Texas Instruments
M. Ricchetti, Synopsys
P. Varma, Veritable

LUNCH: 12:30pm - 1:30pm
INVITED SESSION 1:30pm - 2:30pm
The Prospects of Core Test: VSI Alliance's Manufacturing Test DWG, M. Chandramouli, Synopsys
SESSION 4: 2:30pm - 4:00pm
Advanced Solutions for SOC Testing
Session Moderator: T. Anderson, Pheonix Technologies
4.1 Scan Length Reduction in Cores Using Virtual Scan Chains, A. Jas, B. Pouya, N.A. Touba, University of Texas at Austin
4.2 Space Compaction in Testing Systems on a Chip, B.S. Greene, Synopsys
4.3 A High Level Environment for the Automatic Insertion of HD-BIST Structures, A. Benso, S. Cataldo, S. Chiusano, P. Prinetto, Politecnico di Torino, Italy, Y. Zorian, LogicVision
4.4 Soft Wrapper Design for Embedded Cores Using a System Level Approach, O.P. Dias, J. Semiao, I.M. Teixeira, J.P. Teixeira, INESC, Portugal
Discussion Panel:

S. Bhawmik, Lucent
C.J. Clark, Intellitech
A. Hales, Texas Instruments
A. Orailoglu, UCSD

	REGISTRATION: 2:00pm - 7:00pm
	OPENING SESSION: 4:00pm - 4:45pm Welcome Address - Y. Zorian, General Chair Keynote Address - Philips' Experience in Core-Based Design and Test of System ICs, R. Segers, Philips Semiconductors
	SESSION 1: 4:45pm - 6:45pm Current Practices in System-on-Chip Test Session Moderator: T.W. Williams, Synopsys
	1.1	System-Level-Integration Test Hardware and its Impact on Reuse and Design, F. Muradali, R. Aitken, N. Jaarsma
	1.2	Strategies for Testing Embedded Cores at Cirrus Logic, S. Makar, Cirrus Logic
	1.3	At-Speed Test of a DSP Subsystem Embedded in a Wireless Application Chip, H. Bederr, F. Chirat, Texas Instruments, France
	1.4	A Hierarchical Test Methodology involving Multiple Embedded Cores having Different DFT Mechanisms, M. Spadari, T. Vaida, P. Ghosh, LSI Logic
	Discussion Panel: R. Kapur, Synopsys W. Ke, Cadence M. Nicolaidis, TIMA L. Whetsel, Texas Instruments
	RECEPTION: 6:45pm - 8:00pm
	PANEL SESSION: 8:00pm - 9:30pm CAD Tools for Core Test Co-Organized with: IEEE Design & Test of Computers Moderator: Erik Jan Marinissen, Philips Panelists: Michael Howells, LogicVision Teresa McLaurin, Motorola Maurice Lousberg, Philips ED&T Srinivas Patil, Mentor Graphics Maurizio Spadari, LSI Logic

	CONTINENTAL BREAKFAST: 7:00am - 8:00am
	SESSION 2: 8:00am - 10:00am New Approaches in Testing Embedded Cores Session Moderator: D. Bouldin, University of Tennessee
	2.1	A Method for Path Delay Fault ATPG in Embedded Cores, S. Tragoudas, M. Michael, University of Arizona
	2.2	On Testing of Non-Isolated Sequential Embedded Cores and their Surrounding Logic, I. Pomeranz, University of Iowa, Y. Zorian, LogicVision
	2.3	Microprocessor Based Testing for Core-based System-on-Chip, F. Martin, C. Papachristou, Case Western Reserve University
	Discussion Panel: Training IP Creators and Integrators S. Dey, UCSD D. Gizopoulos, 4Plus M. Lobetti, Italtel R. Rajsuman, Advantest
	COFFEE BREAK and POSTER SESSION: 10:00am - 10:30am Probabilistic IP Verification, R. Drechsler, B. Becker, Albert-Ludwigs-University, Germany A Programmable BIST Compiler for Memory Cores, K-J. Lin, C-W Wu, National Tsing Hua University, Taiwan Testability Verification of Embedded Systems based on Weak Mutation Analysis, F. Vargas, E. Bezerra, A. Terroso, PUCRS
	SESSION 3: 10:30am - 12:30pm Experiences in Testing Reusable Core-based Systems Session Moderator: Rob Roy, Intel
	3.1	Generating Core Test Control Mechanisms, G.E.A. Lousberg, Philips Research, The Netherlands
	3.2	Design for Test in TI's TMS320C27xx: Techniques for Achieving High Fault Coverage in Embedded Cores, B.S.S. Chakravarthy, M.S. Rao, J. Abraham, R.A. Parekhji, Texas Instruments, India
	3.3	The Embedded DRAM Test Dilemma, D. Richter, C. Hoffmann, V. Kilian, Siemens Semiconductors Group, Germany
	3.4	A Virtual Test Approach for Reusable Core Test IP, E. Perkins, M.R. Jones, IMS
	Discussion Panel: R. Aitken, HP D. Bhattacharya, Texas Instruments M. Ricchetti, Synopsys P. Varma, Veritable
	LUNCH: 12:30pm - 1:30pm
	INVITED SESSION 1:30pm - 2:30pm
	The Prospects of Core Test: VSI Alliance's Manufacturing Test DWG, M. Chandramouli, Synopsys
	SESSION 4: 2:30pm - 4:00pm Advanced Solutions for SOC Testing Session Moderator: T. Anderson, Pheonix Technologies
	4.1	Scan Length Reduction in Cores Using Virtual Scan Chains, A. Jas, B. Pouya, N.A. Touba, University of Texas at Austin
	4.2	Space Compaction in Testing Systems on a Chip, B.S. Greene, Synopsys
	4.3	A High Level Environment for the Automatic Insertion of HD-BIST Structures, A. Benso, S. Cataldo, S. Chiusano, P. Prinetto, Politecnico di Torino, Italy, Y. Zorian, LogicVision
	4.4	Soft Wrapper Design for Embedded Cores Using a System Level Approach, O.P. Dias, J. Semiao, I.M. Teixeira, J.P. Teixeira, INESC, Portugal
	Discussion Panel: S. Bhawmik, Lucent C.J. Clark, Intellitech A. Hales, Texas Instruments A. Orailoglu, UCSD