Starting Point for a Scalable Core Test Access Architecture
Based on a
Standardized Core Test Access Port (CTAP)

a) The CTAP will provide a standard serial communication interface that all internal cores must have, at a minimum.

b) The CTAP will require a minimum number of internal bussing signals and IC pins.

c) The CTAP can be used by itself to support core testing and core-to-core interconnect testing based on known test methods such as scan, boundary scan, bist, etc.

d) The CTAP can be used to enable additional internal bussing signals and/or IC pins to expand core testing to meet a particular core vendors private test requirements/methods.

e) The CTAP may be the 1149.1 TAP, less the boundary scan register.

(Giles/Whetsel 4-15-97)

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f) The CTAP will be able to place the core in an isolated state, such that its outputs do not affect other cores and that arbitrary values may be placed on its inputs.

g) Each CTAP will be uniquely addressable. (This needs some definition, particularly for hierarchical cores, but we need to think about possible implementations).

(Aitken 4-25-97)

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h) The CTAP serial communication protocol will be compatible with 1149.1 to allow Core test/emulation/programming schemes to be reused at higher assembly levels (i.e. at MCM, Board, and System levels).

(Whetsel 4-26-97)

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