This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.
There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete — making the test technology less useful for others.
This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices..
| Chair | Heiko Ehrenberg | h.ehrenberg@ieee.org | |
| Vice-chair | Bob Russell | r.russell@ieee.org | |
| Secretary Emeritus | Adam Ley | a.ley@ieee.org | |
| Chair Emeritus | Frans de Jong | ||
| Editor Emeritus | Leon van de Logt |
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