This project will develop a standard protocol for testing the interconnection of low-cost, complex memory ICs where additional pins for testing are not available and implementation of Boundary Scan is not feasible. This protocol will describe the implementation rules for the SCITT test logic in ICs which is needed for testing and describes test mode access and exit. The project is limited to the behavioural description of the implementation and will not include the technical design for the test.
There is currently no defined, independent standard for this new test technology. Each vendor is free in the way of implementing test hardware functionality in their ICs. Without an independent standard, testability is reduced and test coverage may not be complete making the test technology less useful for users. This protocol will provide the necessary implementation rules for highest coverage and diagnosis and for test mode access and exit. It will guide IC vendors to implement and test manufacturers to support this uniform design-for-test method. The standard also allows implementation in devices other than memories. In contrast to IEEE 1149.1 standard this standard provides a static test method, requires less test pins and is lower in costs.
| Chair | Heiko Ehrenberg | he@goepel.com | |
| Vice-chair | Bob Russell | r.russell@ieee.org | |
| Secretary | Adam Ley | a.ley@ieee.org | +1 972 6643015 |
| Chair Emeritus | Frans de Jong | ||
| Editor Emeritus | Leon van de Logt |
contact the Chair for current list