theory

This page gives you an easy understanding of what is being standardized in the working group. The theory is based on the original idea and is, as usual in standardization, subject of change.

For modern, complex memories a test problem arises. Dynamic restrictions (clusters require a high-speed clock) hampers normal interconnection test because the boundary scan circuit can not meet these dynamic requirements. Besides that, chip access follows a complex sequence (often a command register is present allowing configuration of the device). In many cases also an initialization sequence is needed before memory access can take place. Non-volatile memories hampers normal interconnection test because writing into the memory will destroy the functional programmed data. Testing before functionally programming the device is not feasible because of the too long testing time. Memories with these properties are called ‘complex memories’ (e.g. Flash, SDRAM, Rambus devices etc.) The cooperation with Boundary-Scan, in order to enable simple and efficient testing requires some Design-for-Test (DfT) adaptation in these ‘complex’ memories. Random clusters are approached with dedicated test patterns that can propagate through the cluster. Memory clusters know a regular structure and for these, automatic test pattern generation is possible. For memories in general, Boundary-Scan is still not economical to implement. What is SCITT? SCITT requires the insertion of XOR/XNOR circuits in a device. These circuits replace the normal function of a chip when in test mode. It is basically meant for board-level test. The acronym SCITT shows two important aspects: It is about ‘static’ testing. Once in test mode it bypasses the dynamic (parametric and high frequency) properties of the component. It is about component interconnection testing, verifying the connections between the device and its surroundings. SCITT is developed to provide a cheap test solution in combination with Boundary Scan. It is therefore not a substitute for but an addition to Boundary Scan as test solution. It is assumed that the device, which has this test circuitry implemented, can be fully accessed on all its pins at board level. This can be realized, amongst others, by access from an adjacent Boundary Scan device or from direct access from an edge connector.
Boundary Scan access to a memory device The basic idea of SCITT is simple: consider all outputs of a device as outputs of XOR/XNOR circuits. Each output function (pin) must have a unique mapping on the inputs of the device. Furthermore a fail-safe way to get in and out of test-mode is required. The schematic block diagram below shows how to prevent entering the functional block (in this case the SDRAM core) in test mode. In test mode a simple, static, logic (XOR/XNOR) function remains that replaces the original function of the device, as ‘seen’ from it’s pins. This logic function enables easy detection of all single stuck-at and bridging faults that may occur during assembly. Back to Top
Some basics A memory device has three groups of connections, a control bus, an address bus and a data bus. From the control bus a minimal but necessary sub set is selected for SCITT test control. The remaining control connections are combined with the regular inputs (address bus) and together they form the set of extended inputs for the SCITT circuitry. When control outputs are present as well, they are combined with the regular outputs (data bus) to form the set of extended outputs. In this way, for SCITT there is always only a set of extended inputs, connected through the XOR/XNOR functions to a set of extended outputs. Note that the (data) outputs may have a bi-directional functionality. It is stated that the proof of a correct interconnection need only to be made in a single direction. The capability to check the correct functioning of the total I/O buffer after assembly is lost with this method.
		To maximize diagnostics, each XOR/XNOR function must have an odd number of inputs greater than one and each output must have a unique combination of inputs connected (see paper). In test mode, SCITT changes the ‘complex’ memory function into a simple logic cluster containing XOR/XNOR functions. In order to keep test pattern generation simple, the basic set of a walking ‘1’ and walking ‘0’ sequence is applied to the extended set of inputs. Additionally, an all ‘1’ and all ‘0’ pattern complete the set of stimuli. So, the number of used test vectors is also very small. This is a requirement for this technology if it is used with Boundary Scan. If N is the number of extended inputs the total number of test vectors is 2N+2, which is linear with the number of inputs of the memory devices.
When to use SCITT In modern multi media designs, basic elements are mixed signal I/O, a processor and some memory (see figure 4). Memory and mixed signal circuits often lack a test mode that is "compatible" with Boundary Scan. Trends in modern designs also show that processor speed and the amount of memory connected are still increasing. Also more and more "complex memories" are being used. A complex memory is a memory with an embedded protocol or memories that need initialisation before use. Examples are SDRAM, FCRAM, RAMBUS, FLASH, and FIFOs. For the memory market, price and pin compatibility are very important. The silicon overhead and four extra pins needed to implement Boundary Scan are unacceptable.
The protocols and initialisations, together with dynamic access restrictions for the memories, make interconnect testing by means of Boundary Scan from surrounding devices difficult. The difficulty is especially influenced by the Boundary Scan chain length involved (TriMedia has 385 cells). Even with special algorithms, the dynamic memory timing aspects of SDRAM, FCRAM or RAMBUS memories are still to be respected. If a connection is failing, proper access to the devices may be impossible at all, leaving this test option meaningless. SCITT can overcome these problems because of its static nature during test. SCITT needs no or almost no extra pins and requires very little silicon overhead. Perfect diagnosis and detection. The manner in which the XOR/XNOR logic is implemented in a device determines whether or not perfect detection and perfect diagnosis of faults is possible. 'Perfect', however, refers to the fault model used. For SCITT, the fault model includes: Stuck-at faults on inputs and outputs (both stuck-at one and stuck-at zero) Non-overlapping bridging faults between groups of pins (both wired-OR and wired-AND between input pins, output pins and input/output pins) The implementation itself is described in VHDL (in a Scitt Implementation File). SCITT is based on the following rules (see paper) and therefore a SCITT implementation should always be referenced to this rules. Rule 1: SCITT inputs and outputs must be connected Rule 2: No two distinct SCITT outputs are equivalent Rule 3: Buffers (XORs with only one input) are not allowed If your implementation obeys these first three rules, perfect detection of the faults mentioned in the fault model is possible. Rule 4: Invertors (XNORs with only one input) are not allowed Rule 5: Singular inputs are not allowed (one input must influence more than one output) Rule 6: X(N)ORs with an even number of inputs are not allowed If your implementation obeys not only rules 1-3, but also rules 4-6, it allows for perfect detection AND perfect diagnosis of the faults.
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Short overview of the technology.