P-1788:
The voting period herewith
begins. Voting will continue until after Monday, July 29, 2013.
Since some actual text is proposed, voting on this motion will proceed
according to the RULES FOR ACTUAL TEXT. (We are voting on
11.11.11 of the document.) That is,
Comment can continue during voting, but the motion
cannot be changed during voting. That is,
1. a 2/3 majority is necessary for the motion to pass,
2. any NO votes MUST be accompanied by an explanation of and
a corresponding commitment to the changes would cause
the voter to change the "NO" vote to "YES".
Juergen: Please update the web page with this action.
Acting secretary: Please record the transaction in the minutes.
The motion appears in the private area of the IEEE P-1788 site:
http://grouper.ieee.org/groups/1788/private/Motions/AllMotions.html
I have also appended the motion, for your convenience.
As usual, please contact me if you need the password to the private
area.
Best regards,
Baker (acting as chair, P-1788)
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Motion
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1. An implementation of Exact Dot Product EDP and Complete Arithmetic
CA be no longer required by P1788. They should be treated as a
recommended way to achieve the broader aim of evaluating highly
accurate sums and dot products, which has many uses in interval
computing.
2. The current text on EDP and CA (11.11.11 in the current draft) be
moved to Level 3 with minor revisions and replaced at Level 2 by the
following text:
---start of text---
Reduction operations.
In an implementation that provides 754-conforming interval types,
correctly rounded versions of the four reduction operations sum, dot,
sumSquare and sumAbs of IEEE 754-2008 §9.4 shall be provided for the
parent formats of each such type. If such correctly rounded operations
are provided by the underlying 754 system, these shall be used;
otherwise they shall be provided by the implementation.
Correctly rounded means that the returned result is defined as follows.
- If the exact result is defined as an extended-real number, return
this after rounding to the relevant format according to the current
rounding mode. An exact zero shall be returned as +0 in all rounding
modes.
- Otherwise return NaN.
All other behavior, such as overflow, underflow, setting of IEEE 754
flags, raising of exceptions, and behavior on vectors whose length is
given as non-integral, zero or negative, shall be as specified in IEEE
754-2008 §9.4. In particular, evaluation is as if in exact arithmetic
up to the final rounding, with no possibility of intermediate overflow
or underflow.
Intermediate overflow could result from adding an extremely large
number N of large terms of the same sign. The implementation shall
ensure this cannot occur. This is done by providing enough leading
carry bits in an accumulator, or equivalent, so that the N required is
unachievable with current hardware. [Note: For example, Complete
Arithmetic for IEEE 754 binary64, parameterized as recommended by
Kulisch and Snyder, requires around 2^88 terms before overflow can
occur.]
It is recommended that these operations be based on an implementation
of Complete Arithmetic as specified in §X.Y.
---end of text---