[
Date Prev][
Date Next][
Thread Prev][
Thread Next][
Date Index][
Thread Index]
RE: DPD vs. BID hardware
Nobuyoshi Mori wrote:
The situation for BID is, that there exists no
implementation which is available. We have done the
feasibility study for the BID claims, and we so far
cannot verify the claims. There are many issues, but:
1) lack of 128 bit register in Intel and AMD CPUs.
...
Nobu:
Please see Chapter 10 of Volume 1 of the "IA-32 Intel(r) Architecture
Software Developer's Manual" describing the MMX (64-bit registers) and
SSE (128-bit register) SIMD instruction set:
John Crawford
10.1 OVERVIEW OF SSE EXTENSIONS
Intel MMX technology introduced single-instruction multiple-data (SIMD)
capability into the IA-32 architecture, with the 64-bit MMX registers,
64-bit packed integer data types, and instructions that allowed SIMD
operations to be performed on packed integers.
SSE extensions expand the SIMD execution model by adding facilities for
handling packed and scalar single-precision floating-point values
contained in 128-bit registers. If CPUID.01H:EDX.SSE[bit 25] = 1, SSE
extensions are present. SSE extensions add the following features to the
IA-32 architecture, while maintaining backward compatibility with all
existing IA-32 processors, applications and operating systems.
* Eight 128-bit data registers (called XMM registers) in non-64-bit
modes; sixteen XMM registers are available in 64-bit mode.