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*To*: stds-802-3-10gbt@ieee.org*Subject*: [10GBASE-T] Technical feasibility: power*From*: Keith Vertrees <keith@vativ.com>*Date*: 04 Aug 2003 17:27:04 -0700*In-Reply-To*: <4.3.2.7.2.20030804105848.02292748@fedex.cisco.com>*References*: <4.3.2.7.2.20030804105848.02292748@fedex.cisco.com>*Sender*: owner-stds-802-3-10gbt@majordomo.ieee.org

I've been reading this forum with great interest, and I believe that power is the proverbial elephant in the room here. Others, I think, would agree. In a July 31 email, Xiaopeng wrote: "Due to the complexity increase of the DSP part and the analog part, even using 65nm technology for digital circuit and using SiGe technology for analog circuit, to reach 100m on CAT-7, the estimated power of the transceiver (assume it is practically feasible) will be a number that can surprise you. I believe more and more data will be given in the following meeting to show you the reality." 5 Watts is much, much below the surprising number that I have in mind. If this were going to be a 5 Watt part I would have no worries. Sreen and others have stated that the DSP required for 10G would require 6.7 times as many taps as a 1G Phy. And those taps will be running 6.7 times as fast (833 MHz vs. 125 MHz). Therefore the power increase is around 44X. Others have claimed that a 10G Phy could be implemented with many fewer gates but have not, as far as I can tell, provided any evidence to support this claim. Let's assume that today's 750 mW 1G Phy dissipates 400 mW of DSP power. That means the digital portion of a 10G Phy, in today's .13u technology, would dissipate 17W. With respect to analog power, the presentation at the following URL http://grouper.ieee.org/groups/802/3/10GBT/public/mar03/jones_2_0303.pdf mentions the TC1200 ADC from Telasic (for reference, the URL is http://www.telasic.com/live/products/10bit1GSPS.shtml ). The presentation lists the TC1200 at 10 bits of resolution with 8 bit ENOB. From Telasic's website, the TC1200 consumes 5.5 W. A 10G Phy would require 10 bit ENOB, and would require 4 ADCs. Assuming a very efficient future implementation of a 10 bit ENOB ADC would dissipate the 5.5W that today's 8 ENOB ADC dissipates, we're talking about 22W for the ADCs alone. Let's assume 2 more Watts for the remaining analog circuitry. Suppose we can reduce the 17W of digital power by a factor of 4 with two process shrinks (to 65 nm in around 5 years). That's 4W of digital power dissipation. So we're talking about 24W of analog power and 4W of digital power in a "future" (5 years hence) Phy, a whopping total of 28W! I would argue that this level of power dissipation materially affects the technical feasibility of the program, and therefore must be considered before it leaves the Study Group phase. -- Keith Vertrees Vativ Technologies, Inc. Vice President of Engineering 4350 Executive Drive, Ste. 200 Voice (858)362-0850 San Diego, CA 92121 Fax (858)362-0855 keith@vativ.com

**References**:**RE: [10GBASE-T] Technical feasibility: power***From:*Bruce Tolley <btolley@cisco.com>

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