Re: [10GBT] Simulated Performance of RS (2048,1723) LDPC code
You are assuming PAM2 blocks in your calculations. We were running PAM8
simulations, and therefore, the number of information bits per block is 2747
bits (not 1723 bits), and the number of coded bits is 3072.
The 18 errored bits occured over 2 blocks and only in the 12-bit fixed point
simulations and not in the floating point simulations. Finally, there were
no blocks that needed more than 12 iterations for the algorithm to converge.
>From: Scott Powell <firstname.lastname@example.org>
>Subject: Re: [10GBT] Simulated Performance of RS (2048,1723) LDPC code
>Date: Fri, 17 Sep 2004 11:06:43 -0700
> I must have something wrong with my math, I'm not getting 20 trillion
>(20e12) info bits from your numbers:
>(7,302,369,000 blocks)*(1723 bits/block) = 12.58e12 information bits
>If this is correct, the BER would be (18 errors)/(12.58e12 info bits) =
>1.4e-12. Close, but not quite yet to our goal.
>Also, could you tell us:
>1) how many bits you used in your fixed point arithmetic ?
>2) how many iterations were used in the simulations ?
>3) how many block errors resulted in the 18 bits errors ?
> - scott
>Dr. Scott Powell
>Senior Manager, Ethernet PHYs
>From: email@example.com [mailto:firstname.lastname@example.org] On
>Of sailesh rao
>Sent: Friday, September 17, 2004 8:39 AM
>Subject: [10GBT] Simulated Performance of RS (2048,1723) LDPC code
>We have just completed Sum-Product Algorithm simulations of the RS
>(2048,1723) LDPC code at an SNR of 19.9dB with the PAM8 constellation. The
>simulations were conducted both in 12-bit fixed point arithmetic using
>4096-word lookup tables and in floating point arithmetic.
>For 7,302,369,000 blocks at an SNR of 19.9dB, corresponding to 20.06
>trillion information bits and 22.43 trillion coded bits, there were 18 bit
>errors using fixed point arithmetic (for a mean BER estimate of 8.9E-13)
>0 bit errors using floating point arithmetic.
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