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Re: [10GBT] Framing question



Brett,

Thanks for the explanation.

Should the FrameSync be 4 bits, and not 14 bits as indicated in that slide?

Sailesh.

>From: Brett McClellan <bmcclellan@SOLARFLARE.COM>
>Reply-To: Brett McClellan <bmcclellan@SOLARFLARE.COM>
>To: STDS-802-3-10GBT@listserv.ieee.org
>Subject: Re: [10GBT] Framing question
>Date: Wed, 6 Oct 2004 08:51:52 -0700
>
>Sailesh,
>
>It's clear in the diagram that 825 bits are designated to be encoded by the
>LDPC encoder.
>So, 825 bits + 8 pad bits are encoded by LDPC (1024,833) to generate 191
>parity check bits.
>The total coded bits are 825 + 191 = 1016.
>There are 127 4DPAM12 symbols and each carries 8 coded bits, 127 * 8 =
>1016.
>
>Brett
>
>
>-----Original Message-----
>From: stds-802-3-10gbt@IEEE.ORG [mailto:stds-802-3-10gbt@IEEE.ORG]On
>Behalf Of sailesh rao
>Sent: Wednesday, October 06, 2004 4:24 AM
>To: STDS-802-3-10GBT@listserv.ieee.org
>Subject: [10GBT] Framing question
>
>
>Hi All,
>
>The available coded bits in the framing shown on slide 17 of
>tellado_1_0904.pdf can be computed as
>
>Number of PAM symbols: 1 4DPAM2 + 1 4DPAM12 + 126 4DPAM12T
>Number of coded bits:       4bits      +    8 bits       + 126*8 bits
>           = 1020 bits
>
>Therefore, how are the remaining 4 bits in the 1024 LDPC block being
>modulated?
>
>Thanks,
>Sailesh.
>srao@phyten.com
>
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