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Re: [10GBT] Framing question


Assuming the PAM2 FrameSync has the two levels {-7,+7}, which are a
subset of the PAM12 levels {-11,-9,-7,-5,-3,-1,1,3,5,7,9,11}, then a
PAM12 modulator can generate a PAM2 sequence using the appropriate 14
bits values. Thus the 14 bits in tellado_1_0904 represented the
equivalent number of PAM12 bits, although we can also use 4 bits to
specify PAM2 over each of the 4 wires if the PAM modulator treats the
first symbol differently


-----Original Message-----
From: stds-802-3-10gbt@IEEE.ORG [mailto:stds-802-3-10gbt@IEEE.ORG] On
Behalf Of sailesh rao
Sent: Wednesday, October 06, 2004 4:57 PM
Subject: Re: [10GBT] Framing question


Thanks for the explanation.

Should the FrameSync be 4 bits, and not 14 bits as indicated in that


>From: Brett McClellan <bmcclellan@SOLARFLARE.COM>
>Reply-To: Brett McClellan <bmcclellan@SOLARFLARE.COM>
>Subject: Re: [10GBT] Framing question
>Date: Wed, 6 Oct 2004 08:51:52 -0700
>It's clear in the diagram that 825 bits are designated to be encoded by

>the LDPC encoder.
>So, 825 bits + 8 pad bits are encoded by LDPC (1024,833) to generate
>191 parity check bits.
>The total coded bits are 825 + 191 = 1016.
>There are 127 4DPAM12 symbols and each carries 8 coded bits, 127 * 8 =
>-----Original Message-----
>From: stds-802-3-10gbt@IEEE.ORG [mailto:stds-802-3-10gbt@IEEE.ORG]On
>Behalf Of sailesh rao
>Sent: Wednesday, October 06, 2004 4:24 AM
>Subject: [10GBT] Framing question
>Hi All,
>The available coded bits in the framing shown on slide 17 of
>tellado_1_0904.pdf can be computed as
>Number of PAM symbols: 1 4DPAM2 + 1 4DPAM12 + 126 4DPAM12T
>Number of coded bits:       4bits      +    8 bits       + 126*8 bits
>           = 1020 bits
>Therefore, how are the remaining 4 bits in the 1024 LDPC block being
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