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[10GBT] Clashing clause 45 registers for 802.3an, ap, aq

Dear participants of IEEE P802.3an, P802.3ap and/or P802.3aq task forces,

Each of these task forces thinks it will use some of the same registers to define e.g. their PMD type.  We need to resolve the conflicts.  I have put comments addressing this issue into each task force.  Petre Popescu has also made input on this topic.

What follows may not be the right answer, but so that all the task forces see the same information:
Bit 1.11.1 in the 10G PMA/PMD extended ability register is used to mean both 10GBASE-KX4 and 10GBASE-T. At least one must change.  10GBASE-LRM nearly took it too.

My suggestion for this table is as follows:
1.11.1 10GBASE-T   (as in .3an D1.2.  .3ap D0.7 has 10GBASE-KX4)
1.11.2 10GBASE-KR  (as in D0.7)
1.11.3 10GBASE-LRM
1.11.4 10GBASE-KX4
1 0 0 0 in the 10G PMA/PMD control 2 register (table 45-8) is used to mean both 10GBASE-T and 10GBASE-KX4.  At least one must change.

With the current projects, we will have a total of 12 10G PMDs to map into this register, so using 5 bits (32 possibilities) to keep to a reasonably logical mapping seems a reasonable compromise between 'logicality' and packing density, allowing for efficient and easier-to-maintain firmware.  One (not the only) suggestion is as follows (this is not an "official position" of any task force).
Noting that before these new projects, 'X4' PMA/PMDs end in 0 0, and serial optical PMDs use the last two bits to represent wavelength.  We then have to decide where 10GBASE-KR goes: I suggest in the '... 0 0' set as we don't know how many future EDC-enabled optical PMDs may appear.  In the proposal below, bits 4 and 3 could be reversed.
1.7.15:5    Reserved
1.7.4:0     as below:
0 1 0 0 0   10GBASE-KX4 (or 10GBASE-T)
1 0 0 0 0   10GBASE-T (or 10GBASE-KX4)
1 1 0 0 0 ? 10GBASE-KR                 (.3ap D0.7 has 10GBASE-KR at 1 0 0 1)
0 1 1 1 0   10GBASE-LRM (or 1 0 1 1 0)
0 0 x x x   All already used by 802.3ae and 802.3ak

Notice that P802.3an and P802.3ap propose other new clause 45 registers and bits which should be checked for clashes.  P802.3aq at present is not proposing further new clause 45 registers and bits beyond these two.