Re: [10GMMF] TP-3 Stressors

thank you for this interesting clarification. I agree with your comments and the argumentation you summarize for limiting PIE-D below 4dB. My opinion is that PIE-D is a metric not uniquely related to the pulse shape. Same PIE-D value might be associated to a huge variety of pulses and when PIE-D reaches 4dB among such IPR variety there are a consistent percentage which induce EDC to failure. The work from Robert Lingle has been quite significant in merit. Same PIE-D leads to different higher value of finite length penalty depending on the IPR considered. My experience is that experimentally I related link failure to PIE-D when it exceeded about 4dB.

Your last issue is again relevant: we do not need PIE-D as an absolute metric but we need instead PIE-D to set the percentage of the installed base which can be covered by 10GBASE-LRM. Setting PIE-D to less then 4dB reduces the coverage I guess below 60% of the last 5% worst case fibers, leading to 98% of the installed base.

Thank you for your contribution,

best regards

Stefano

-----Original Message-----
From: owner-stds-802-3-10gmmf@IEEE.ORG [mailto:owner-stds-802-3-10gmmf@IEEE.ORG] On Behalf Of Norman Swenson
Sent: Montag, 18. April 2005 22:40
To: STDS-802-3-10GMMF@LISTSERV.IEEE.ORG
Subject: [10GMMF] TP-3 Stressors

I would like to better understand the position of those advocating a limit of PIE-D in the range of 3.8-4.0 for the TP-3 stressor selection. I believe we can make progress on the reflector versus taking up weekly TP-3 call time to debate this issue.

So far, as I understand the arguments for a PIE-D of 3.8-4.0, they are:

1) Real-world fiber will show dynamic variation in IPR that will degrade equalizer performance compared to that measured with a static TP-3 test, which somehow leads to a cliff in real-world performance if we set the PIE-D value too high in the TP-3 stress test

2) Cost-effective and power-efficient EDC chips can be produced that achieve performance in this range

Argument (1) would seem to push for higher performance requirements in the static TP-3 test, since margin must be built into the static test to allow for unmodeled dynamic impairments.

Argument (2) has been put forward as though there is some fundamental limitation that prevents cost-effective and power-efficient EDC chips from being produced that can equalize PIE-D values higher than 4.0 dB. I am very interested in learning more about the theoretical or experimental basis for concluding that cost-effective, power-efficient EDC chips cannot perform beyond the 3.8-4.0 dB range that has been proposed as a performance metric.

Until recently, the committee has focused on quantitative analysis to determine performance requirements for EDC based on theoretical models and measured data of optical fiber, with an implicit, if not explicit, goal of 99% coverage of 300m OM-1 fibers. Lately, there has been a shift away from considering the percentage of the installed base that can be covered to setting PIE-D objectives independently of coverage requirements. I do not understand the significance of PIE-D requirements if they are not put in the context of the percentage of the installed base that the PIE-D corresponds to. Without such context, the numbers can be arbitrarily chosen without any real-world significance.

Thanks to any who can help me better understand the arguments for setting PIE-D limits to such a low value compared to that required to achieve 99% coverage.