From owner-stds-802-3-hssg@ieee.org Wed Mar 1 17:21 GMT 2000 Received: from gatekeeper.pdd.3com.com (gatekeeper [161.71.169.3]) by isolan.pdd.3com.com (8.9.1b+Sun/8.9.3) with ESMTP id RAA15860; Wed, 1 Mar 2000 17:21:14 GMT Received: from ruebert.ieee.org ([199.172.136.3]) by gatekeeper.pdd.3com.com (Netscape Messaging Server 3.6) with ESMTP id AAA20CB; Wed, 1 Mar 2000 17:19:29 +0000 Received: by ruebert.ieee.org (8.9.3/8.9.3) id LAA04158; Wed, 1 Mar 2000 11:32:48 -0500 (EST) Message-Id: <4.1.20000301082433.00db7f00@smbmail3> X-Sender: jrrivers@smbmail3 X-Mailer: QUALCOMM Windows Eudora Pro Version 4.1 Date: Wed, 01 Mar 2000 08:34:22 -0800 To: jmw , JR Rivers , Vivek Telang , "stds-802-3-hssg@ieee.org" From: JR Rivers Subject: RE: PAM-5, what are your BERs ? In-Reply-To: <4.2.0.58.20000301055952.00a78700@mail.bayarea.net> References: <4.1.20000229180017.00d72bd0@smbmail3> <01BF82B7.070ECDE0@pc24.cicada-semi.com> Mime-Version: 1.0 Sender: owner-stds-802-3-hssg@ieee.org Precedence: bulk X-Resent-To: Multiple Recipients X-Listname: stds-802-3-hssg X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-802-3-hssg-approval@majordomo.ieee.org X-Lines: 54 Status: RO Content-Type: text/plain; charset="us-ascii" Content-Length: 1964 During the course of these discussions, I've seen people use "hard to do in CMOS" as a reason to reject a proposal. I'm not trying to say that someone couldn't/shouldn't build a 10GbE transceiver in CMOS; however, I am questioning the REQUIREMENT that it be built in CMOS at standardization. I've been working on Ethernet products for quite a long time, and every signalling technology has started off with some non-CMOS implementation and eventually been reduced to CMOS. JR At 06:22 AM 3/1/00 -0800, jmw wrote: >JR -- my semi-biased view: > >i contend it can be built in any manufacturing technology that will >deliver the performance required at the cost target you like. a 5-PAM >receiver built of monolithic CMOS can do that nicely, when feature >size is on the order of 0.18um to 0.25um, and there are more than >a few foundry service houses that can offer that geometry scale >(which is a critical concern for 'fabless' semiconductor houses). >BiCMOS and GaAs both outperform CMOS at the serial line rate, >but neither of them is as widely available nor can they compete as >well in complex back-end signal processing functions -- equalization, >error correction, general DSP. > >it is my impression that many new products start in one technology >(probably for "time to market" issues) but eventually wind-up in CMOS. > >finally, there are probably many ways one can build a fast ADC but >the more difficult challenge -- for 10Gbd x-PAM -- is in building a fast, >linear DAC. > >and now, back to morning coffee... >-- >J M Wincn >P O Box 631 >Cupertino, CA 95015-0631 >Email: jmw@bayarea.net >Voice: 408-725-0846 >Fax: 408-873-0293 >Cell: 408-394-5283 > >At 06:02 PM 29-02-2000 -0800, JR Rivers wrote: > >>Not to throw water on an oil fire, by why does the transceiver have to be >>CMOS? If my memory serves me correctly, most of the SERDES devices used in >>GE were BiCMOS or GaAs until recently. >> >>JR > >