- To: stds-802-3-hssg@xxxxxxxxxxxxxxxxxx, kardontchik.jaime@xxxxxxxxxxx
- Subject: 10G-BASE-T
- From: Kardont@xxxxxxx
- Date: Fri, 21 May 1999 07:20:18 EDT
- Sender: owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx
I would like to throw in another proposal to the many already on the table. I
call it 10G-BASE-T for reasons that will become clear below.
This proposal has the following advantages:
1) It uses the smallest proposed switching rate till today: 1.25 GHz. This
simplifies the requirements on the electronics (that could be implemented
using standard CMOS) and the optical components.
2) It steals the Physical Coding Sublayer (PCS) from a finished Ethernet
standard: 1000BASE-T, saving easily 2 years in standards' development.
3) The PCS of 1000BASE-T has a minimum overhead since it uses scrambling. It
also provides an additional 6 dB signal gain using Viterbi encoding/decoding.
(Viterbi decoding in 10Giga would be trivial since there is no need for an
equalizer in the 10Giga receiver). Other advantages of the 1000BASE-T PCS
applicable to 10Giga are that it provides easy correction for differential
delay and polarity inversion. Correction for differential delay (or skew) was
necessary in 1000BASE-T because it runs on 4 pairs of Copper cable.
Correction of skew might be also needed in 10Giga when different wavelengths
are used on the same optical fiber.
4) It uses MAS (5-PAM) and 4-WDM in the optical medium to keep the optical
rate at 1.25 GHz.
A simple schematics of the data flow follows (I hope that the drawing does
not get corrupted during transmission):
| 10G-MII |---/--->| PCS |---/--->| W1,W2,W3,W4 |-------->
(a) (b) (c) (d)
(a) 8 wires carrying 1.25 Gbps data each, from the MII to the PCS
(b) CMOS chip implementing the 1000BASE-T PCS at 1.25 GHz
(c) 4 wires carrying each 2.5 Gbps data using 5-PAM. In reality only 4-PAM is
needed to carry 2.5 Gbps data. The additional fifth level is needed to add
non-data symbols, like IDLEs, start-of-frame and end-of-frame.
(d) 4 optical transmitters carrying 5-PAM (MAS) at a rate of 1.25 GHz each,
using 4 different wavelengths: w1,w2,w3,w4.
(e) 1 optical fiber carrying the 4 optical wavelengths.
a) The 10Giga MII interface is identical to the 1 Giga Ethernet MII
interface, but it runs 10 times faster, with each wire carrying 1.25 Gbps,
for a total of 1.25*8 = 10 Gbps.
b) The MII goes to a CMOS chip that implements the PCS of 1000BASE-T, but at
a rate 10 times faster, that is, 1.25 GHz.
c) The output of the CMOS chip has 4 transmitters, each one using 5-PAM
levels at 1.25 Gbaud/sec each (the same as 1000BASE-T, but at a rate 10 times
faster). The 5-PAM logic levels will be shaped (or translated) into
appropriate analog waveforms to be used by the next stage, the optical
transmitters (see Transcendata's presentation in the 802 Plenary, March 99).
d) these 4 data streams go to 4 lasers that use MAS
(Multi-Amplitude-Signalling). Each laser transmits at a different wavelength
(w1,w2,w3,w4) and at a 1.25 GHz symbol rate.
e) the four optical streams are merged into one optical fiber carrying the 4
Jaime E. Kardontchik
San Jose, CA 95131