RE: PHY I/F, placement of decoder/encoder
- To: "'Haim Shafir'" <hshafir@xxxxxxx>, stds-802-3-hssg@xxxxxxxxxxxxxxxxxx
- Subject: RE: PHY I/F, placement of decoder/encoder
- From: Curt Berg <cberg@xxxxxxxxxxxxxxxxxxx>
- Date: Tue, 25 May 1999 11:01:12 -0700
- Cc: oprescu <oprescu@xxxxxxxxxxxxxx>
- Sender: owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx
I recommend that the PHY interface use a
signaling compatible with EIA/JEDEC JESD67.
Basically a "LVTTL" that is can configured
for different VDD voltages. If we also
mandate an impendance matched/controlled driver,
+/- 10%, unterminated point to point <12 inch traces,
we should easily be able to do 300+Mbaud per wire.
Extreme Networks, cberg@xxxxxxxxxxxxxxxxxxx
From: Haim Shafir [mailto:hshafir@xxxxxxx]
Sent: Tuesday, May 25, 1999 9:49 AM
Subject: PHY I/F, placement of decoder/encoder
Currently the 8/10B encoder/decoder
is located in the PHY.
The current implementation of 2.5Ghz and 10Ghz
do not have those function on board
In addition the current chips are GaAs, Bipolar
or SiGe ( in the near future )
If you place more logic on those chips you will
burn a lot of power, with 4 channels you could fry
and egg. ( those chips already burn Watts )
So we strongly suggest that any decoding/encoding/
alignment function should reside on the ASIC side.
Now the next big problem is the interface
if we run it at 2.5/8 or 2.8/10 times 4
we will have 32 lines single ended
or 64 differential. The current diff interfaces
all burn tons of power , LVDS , PECL all are power hogs.
With single ended you get bad switching noise
the ASIC can handle it but I am not sure about
a 4 port transceiver.
We may want to look at CML type interface.
But again we need to look at current implementation
( at no preferred order : AMCC, Vitesse , Maxim ... )
and check what is available out there and also
see what is available on the ASIC side.
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