RE: 1000BASE-T PCS question
- To: rtaborek@xxxxxxxxxxxxxxxx, dwmartin@xxxxxxxxxxxxxxxxxx
- Subject: RE: 1000BASE-T PCS question
- From: bin.guo@xxxxxxx
- Date: Thu, 27 May 1999 16:28:23 -0700
- Cc: stds-802-3-hssg@xxxxxxxx, sachs@xxxxxxxxxxxxxx, "widmer@xxxxxxxxxx widmer@xxxxxxxxxx widmer"@us.ibm.com
- Sender: owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx
The DC balance can be directly translated into jitter (when timing is
concerned) and offset (when threshold slicing is concerned). You only need
to deal with the former if the signal is 2-level NRZI, while you need to
deal with both if multi-level signal modulation is used.
For long term DC imbalance, it translates into low frequency jitter and if
it's low enough(<1 KHz ?), it's called baseline wonder. For short term, it
relates to Data Dependent Jitter, which is more difficult for timing
recovery to handle since it's not from system or channel imparity, and
therefore it's harder to compensate.
When you have a lot of jitter margin, for example in lower speed clocking,
the amount of jitter, translated from DC drift resulted from data imbalance
coupled by AC circuit, percentage wise is a small portion of the clock
period and therefore does not contribute to much of the eye closing. On the
other hand, for high speed clocking at 10G (100 ps?), the jitter translated
from the same amount of DC drift can be a significant portion of the clock
period, so contributes to much large percentage wise jitter which results in
reduced eye opening -- higher BER.
Dave said in his mail that "The limiting factor is enough RX optical power
to provide a sufficiently open eye." but you still have to deal with the
data dependent jitter due to DC imbalance generated after O/E, that can
close the eye further again.
> -----Original Message-----
> From: Rich Taborek [SMTP:rtaborek@xxxxxxxxxxxxxxxx]
> Sent: Thursday, May 27, 1999 3:23 PM
> To: David Martin
> Cc: HSSG_reflector; Sachs,Marty; Widmer,Albert_X
> Subject: Re: 1000BASE-T PCS question
> Do you know of any research or other proofs in this area? You say that
> lower speed SONET links regularly achieves BERs of < 10 E-15. I have
> substantial experience with mainframe serial links such as ESCON(tm)
> where the effective system BERs are in the same ballpark. SONET uses
> scrambling with long term DC balance and ESCON uses 8B/10B with short
> term DC balance. The following questions come to mind:
> - How important is DC balance?
> - How does this importance scale in going to 10 Gbps?
> I'll see if I can get some 8B/10B experts to chime in here if you can
> get scrambling experts to bear down on the same problem.
> >(text deleted)
> >The point here is that the SONET scrambler is not the limiting issue in
> >achieving low error rates. The issue is having enough photons/bit, or
> >optical SNR (eye-Q) to accurately recover the data.
> >David W. Martin
> >Nortel Networks
> >+1 613 765-2901
> >+1 613 763-2388 (fax)