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Re: [Fwd: 1000BASE-T PCS question], Importance of DC Balance

How important is DC Balance? This question is best answered by the engineers who
design the critical three circuits (Laser Driver, Receiver Preamplifier, Clock
Recovery), the persons who package the electrical and optical components, and
those who design the verification and production tests. Given an option, they
generally prefer a code with DC balance and a short run length. After
consultation with colleagues active in those endeavors, I can offer the
following list of circuit related advantages of a transmission code such as the
Fibre Channel 8B/10B code:
   Level settings of the laser driver bias point  and the receiver threshold can
   be based on the average signal level which is simpler and more precise than
   using level restoring circuits. The receiver level restore circuits usually
   require some type of peak detection circuits which are difficult to implement
   if the electronics is pushed to its limits. Peak detector noise may cause
   higher noise levels than otherwise expected because of the peak detectors
   tendency to capture occasional large noise excursions. The design of a peak
   detector which is both accurate and fast requires difficult inherent
   Thermal cycling of lasers or LED's is eliminated.
   Capacitive coupling  and level shifting is possible without complications to
   accommodate various package, grounding, and power supply configurations at
   the transmitter or receiver. At frequencies above 5 GHz it is hard to find
   capacitors which work well with unbalanced bit patterns for various reasons.
   Capacitive differential coupling at the front end of optical receivers with
   small integrated capacitors is more easily accomplished and provides better
   noise margins. At the lower data rates, designers may still include offset
   compensation circuits with a balanced code to reduce the capacitance values
   to a range compatible with integration in monolithic circuits. Such
   compensation circuits require less precision and complexity for a balanced
   Receivers at the end of computer or LAN links generally require a large
   dynamic range which is more readily achieved with a balanced code.
   Attenuation in electrical package interconnects is on the order of 1 dB/cm at
   the fundamental frequency of 10 GHz and much higher for the frequencies
   needed to transmit fast pulse edges. Any transmission line is easier to
   equalize for balanced codes because of the lower ratio of the maximum to
   minimum frequency content.
   It is desirable to set the low frequency cutoff of receivers as high as
   possible to remove noise from several   sources, such as: power supply noise,
   low frequency modal noise arising from movements of multimode fibers, or 1/f
   noise of front end devices, especially GaAs devices not optimized for low
   noise analog operation . For low and moderate cost highly integrated designs
   it is usually not possible to pick the best devices which otherwise might be
   The shorter run length of a good code allows much relaxed specifications for
   the clock recovery circuit. The lower Q of the PLL enables it to cope with
   more external noise interference such as digital noise coupling from
   neighboring circuits, power supply variations,  or totally external
   electromagnetic interference. It is less problematic to place a  PLL with a
   lower Q on a large digital chip with limited isolation for a fully integrated
   solution. The low pass filter of the PLL is more readily implemented with an
   on-chip capacitor or a totally digital solution (random walk filter) and the
   phase comparator is simpler for the coded version.
   For links carrying scrambled traffic, the link jitter budget expressed as a
   percentages of a baud interval  allows much less jitter for the transmitter
   which significantly complicates the design of the frequency synthesizer, the
   laser driver, and the connection between the driver and the laser.
   Simpler circuits consume less power in a critical area.
   Scrambled data requires nearly ideal circuit implementations in the areas
   discussed above. Cost considerations, design time  and skill limitations make
   the attainment of near perfection for the 10 Gb Ethernet application an
   unrealistic goal. Less than perfect circuits have a greater hidden cost in
   terms of signal to noise ratio for scrambled data. For a given baud and error
   rate, the coded link can span a longer distance with less sophisticated
   The design, performance simulation, test, and trouble shooting is simplified
   for a well constrained code. The robust operation of the coded link depends
   on no assumptions about the data pattern of the traffic. The performance can
   be proven with a few well defined worst case patterns tailored for stressing
   the major performance parameters. There is no exposure to hacking via the
   data pattern. This is in contrast with scrambled links for which performance
   in practice  can only be verified for a statistical consensus pattern and
   where it is always possible to come up with data patterns which cause the
   system to fail.