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RE: interface


It may not be as bad as you think, although your concerns are well

First of all, the 10GbE interface specification should be based on LAN, or
similar to GbE specification, of which the clock tolerance does not need as
tight as SONET for WAN.  When the data are transferred from datacom to
telecom (or vise versa), we need a switch to controvert data anyway;
therefore, we do not have to impose unnecessary tight specification to LAN

As we discussed on reflector before, from PCB layout point of view,
single-ended trace at 300 Mbps can be done, and is cost-effective, although
it will need very careful PC run design to control data skew and reflection.

To design 32 lines of differential pairs on a densely crowded interface area
on a PCB may defeat its purpose.  The reason, in addition to the
single-ended design concerns, the differential pair need to be kept in the
same length, impedance control, cross-talk control, and may need
terminators.  Usually, for an optimum PCB design, there is not enough space
for those requirement; as a result, the PCB layout will compromise quality
and cost-effectiveness to fit them.

I believe single-ended interface is cost-effective, and reliable.  

Ed Chang
Unisys Corporation         

-----Original Message-----
From: Haim Shafir [mailto:hshafir@xxxxxxx]
Sent: Wednesday, June 09, 1999 11:16 AM
To: stds-802-3-hssg@xxxxxxxx
Subject: interface

The main design problem with the interface
is not the ASIC but the switching noise impact
on the jitter performance of the XCVR PLL.

Currently all 2.5Ghz SONET XCVRs on the market
use 8 ir 16 bit diff LVDS interface. I am not
sure if it is possible to meet SONET jitter spec using
32 bit single ended interface.

By choosing a single ended interface 
you limit your transmitter and receiver performance
and you limit the distance 10GBE can span.
I suspect that long distance 10GBE will have
to use a fully differential interface.
Haim Shafir
e9 Inc.
PH 408-343-0192 cell 408-892-1838 fax 408-873-2642