- To: Haim Shafir <hshafir@xxxxxxx>, "Chang, Edward S" <Edward.Chang@xxxxxxxxxx>, stds-802-3-hssg@xxxxxxxx
- Subject: RE: interface
- From: "Chang, Edward S" <Edward.Chang@xxxxxxxxxx>
- Date: Wed, 9 Jun 1999 13:55:31 -0400
- Sender: owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx
The 10GbE clock always uses local clock, but not regenerated clock from
received data; as a result, it does not have to worry about jitter-transfer,
-tolerance, and -generation -- a point to point straightforward design.
Furthermore, the interface data movement is a synchronous design, we do not
worry about the spreading of the switching nose which is synchronous to the
clock -- as long as there are enough set-up time and hold time. However,
the chip should be able to sustain the worst case current flow by the worst
case data pattern. The chip designers are very knowledgeable in dealing
with those issues.
From: Haim Shafir [mailto:hshafir@xxxxxxx]
Sent: Wednesday, June 09, 1999 12:29 PM
To: Chang, Edward S; stds-802-3-hssg@xxxxxxxx
Subject: RE: interface
I am not worried about the PCB
more worried about internal substrate
noise in the PHY chip.
It is true that since 10GBE will be
point to point with re timing in each node
you need not worry about jitter transfer spec
but still 32 buffers switching may kill the PLL performance.
We may want to allow in the spec
some way of spreading out the switching noise
within the bit window.
communication and there is not jitter tranfer spec
At 12:11 PM 6/9/99 -0400, Chang, Edward S wrote:
>It may not be as bad as you think, although your concerns are well
>First of all, the 10GbE interface specification should be based on LAN, or
>similar to GbE specification, of which the clock tolerance does not need as
>tight as SONET for WAN. When the data are transferred from datacom to
>telecom (or vise versa), we need a switch to controvert data anyway;
>therefore, we do not have to impose unnecessary tight specification to LAN
>As we discussed on reflector before, from PCB layout point of view,
>single-ended trace at 300 Mbps can be done, and is cost-effective, although
>it will need very careful PC run design to control data skew and
>To design 32 lines of differential pairs on a densely crowded interface
>on a PCB may defeat its purpose. The reason, in addition to the
>single-ended design concerns, the differential pair need to be kept in the
>same length, impedance control, cross-talk control, and may need
>terminators. Usually, for an optimum PCB design, there is not enough space
>for those requirement; as a result, the PCB layout will compromise quality
>and cost-effectiveness to fit them.
>I believe single-ended interface is cost-effective, and reliable.
>From: Haim Shafir [mailto:hshafir@xxxxxxx]
>Sent: Wednesday, June 09, 1999 11:16 AM
>The main design problem with the interface
>is not the ASIC but the switching noise impact
>on the jitter performance of the XCVR PLL.
>Currently all 2.5Ghz SONET XCVRs on the market
>use 8 ir 16 bit diff LVDS interface. I am not
>sure if it is possible to meet SONET jitter spec using
>32 bit single ended interface.
>By choosing a single ended interface
>you limit your transmitter and receiver performance
>and you limit the distance 10GBE can span.
>I suspect that long distance 10GBE will have
>to use a fully differential interface.
>PH 408-343-0192 cell 408-892-1838 fax 408-873-2642
PH 408-343-0192 cell 408-892-1838 fax 408-873-2642