RE: Leveraging OC-192c
The standard says that the MAC transmits. However, most implementations
have the clock rate determined by the PHY/PMD.
In the CSMA/CD case, the precise relationship of the timings is
very important. In the full duplex link case, with no CS, no MA and no CD,
fewer of the timings are as important.
In the simpler case now being addressed, the actual signalling clock rate
has to be close enough at the two ends to transfer information. The
IFG has to be enough to take care of clock tolerancing and system overheads.
The PAUSE time should have an agreed upon interpretation. I see the
possibility of decoupling the first clock rate from the tick size used
in the latter two timers. I previously mentioned the possibility of
expressing those timers at 10Gb/s ticks, independent of the signalling
rate used on the link itself.
Given a common signalling rate, another agreement between the two
ends of course has to be the packet format and framing. There will be
tradeoffs here of signalling speed, throughput and complexity, which
we should not overlook during these exchanges about the advantages
of using OC-192 regenerator equipment.
From: Grow, Bob [mailto:bob.grow@xxxxxxxxx]
Sent: Tuesday, July 27, 1999 11:01 AM
To: 'Hon Wah Chin'; 'stds-802-3-hssg@xxxxxxxx'
Subject: RE: Leveraging OC-192c
I disagree with your assumption about flow control being an implementation
issue because we are not dealing with an exposed interface. The direct link
of MAC/PLS data rate to the PHY data rate is pervasive in the standard. If
we choose to allow these two rates to differ, we must have a clear
specification of how that works within the standard. If the rate
compensation is not on an exposed interface an implementer does have the
flexability you write of, but 802.3 cannot push the problem off as
In the standard the PHY doesn't clock information from the upper protocol
layers, MAC transmits a serial data stream through MAC/PLS service
interface primitives (it can use PHY signals to determine when to start
transmitting), which (in later generations) is converted to a parallel
nibble or byte stream by the reconcilliation sublayer which in turn is
signalled to a data rate locked PHY across a media independent interface.
While most of the interfaces between these architectural components are not
exposed, being rigorous about their definition has in my opinion been one of
the important ingredients to ethernet's success.
From: Hon Wah Chin [mailto:HWChin@xxxxxxxxxxxxxxxxxxx]
Sent: Monday, July 26, 1999 10:51 AM
Subject: Leveraging OC-192c