Reflectors can be quite confusing some times... Which thread are we
discussing this issue on?
My comments are in context below.
> 3. Requiring an additional clock for the 10 Gb/s side would still not be a
> very significant cost compared to the rest of a 1/10 Gb/s Ethernet switch.
When designing a 10/100/1000/10,000 product, its nice if I can use a single
clock domain for the ASIC that performs the switching... It's not
just nice, it is EXTREMELY nice.
Right now, we are using 125MHz clock domains that are running 10 bits wide
for gigabit and 1 bit wide for 100 megabit. Transferring data
between MACs only involves a width conversion, not a frequency
conversion. Its true that our receivers will have to adapt to frequency
differences on the order of 100ppm, but in some implementations, that is
done by the PHY chips and thus makes our ASICs less complex which we like.
When we move to 10.0000Gbps, it would be nice if we could simply do
a width conversion once again and not have to deal with a substantially
different clock rate at the MAC/PLS interface. We can let the PHYs do the
frequency multiplication with PLLs that they do so well.
This is not an issue of the material cost of an additional crystal
oscillator, it is an issue of development effort required to deal with
multiple clock domains in an already complicated ASIC design.
I hope this clarifies the reason some of us are wanting an integral
clock relationship between 1Gbps and 10Gbps Ethernet.
BTW: I am fully supportive of having a 9.xxxx PHY that allows connection
to WAN links and utilizes gopher-bait or dark wavelengths. I just want to
put the complexity for that solution where it belongs, at the PHY.