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Re: Proposal for accomodating 10.0000 and 9.58464 line rates

"DOVE,DANIEL J (HP-Roseville,ex1)" wrote:

> ... (stuff deleted)
> > Jumping back to implementation, the HOLD signal presents two long term
> > headaches:
> >
> > 1) The most scarce resource is pins, not gates. Do we really want to
> > increase the number of per port pins? - Ariel
> We are talking about 1 pin. I agree that pins are valuable, but usually this
> is an impact for multi-port designs where the number of ports is high and
> cost per port is sensitive to the $.01/port levels. - Dan
> > 2) As soon as technology permits, implementations integrate the PCS
> > coding layer, and eventually the clock recovery and transceiver. The
> > MII ceases to be an exposed interface. For the mainstream MII functions
> > like COLLISION (R.I.P.) and CARRIER SENSE, the event/encoding that
> > defines the function is well defined at the PCS layer and there is no
> > loss of functionality.
> >
> > How do I preserve the HOLD functionality for a hypothetical 10GbE
> > MAC-PCS ASIC (with no MII) that I'll buy three years from now? - Ariel
> If your ASIC incorporates an OC-192 PHY, you will incorporate the flow
> control inside your ASIC. In GbE, there is a different PCS for 1000BT than
> for LX, SX or CX. If we end up with multiple PHYs, some of which run at
> 10.0000 and others that run at 9.58464, it is VERY unlikely that you will
> want to integrate down to the PCS level any more than the likelihood that
> we will be integrating 1000BT PCS into our MAC ASICs on GbE.
> With all of this said, I am not really very religious about the METHOD
> we use to support multiple PHY speeds. I proposed the "hold" signal as
> a compromise proposal to move the standard forward and allow support for
> 10.0000 MAC/PLS interface with OC-192 compatible PHYs.
> It appears that we have multiple methods for doing this available to us
> now. Can we at least agree that a 10.0000 MAC/PLS has concensus now?

I'm strongly in support of Dan Dove's assertion immediately above. I agree that
this is the case and also that an additional method of supporting OC-192 links
is via 802.3x flow control. That being said, I'd like to comment on the issue of

1) It is my suspicion that a 10 GbE/OC-192 PHY will be a highly integrated
animal eventually winding up as two units: A single or multi-port
MAC/PHY chip and a transceiver which may contain a significant amount of the PHY
sublayers. The interface between these two is currently under discussion and has
been proposed as either a quad-serial or many-signal (e.g. 16) parallel. The key
point I'd like to make here is that the PHY itself would likely be the SAME for
each PMD variant. For example, a 10 km LX PMD would support both a data rate of
10.0 Gbps and 9.58464. Is there anyone out there that would rather pay a premium
for one data rate over the other?

2) A minor point: If (1) above is true, then HOLD is implemented as a
gate/signal, not a pin.

> Thanks,
> Dan Dove


Best Regards,

Richard Taborek Sr.    Tel: 650 210 8800 x101 or 408 370 9233
Principal Architect         Fax: 650 940 1898 or 408 374 3645
Transcendata, Inc.           Email: rtaborek@xxxxxxxxxxxxxxxx
1029 Corporation Way    
Palo Alto, CA 94303-4305    Alt email: rtaborek@xxxxxxxxxxxxx