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RE: HARI Systems Design


I revisited your November presentation, "Feasibility of 3.125 Gbps in
CMOS".  The feasibility was well presented, and impressive.  Again, as you
mentioned, it was a "Feasibility" data, but not the qualification test data,
which are quite different as we know.  From feasibility test to
qualification test is a big gap.  Further more, your presentation was aimed
at the CMOS chip, but not the FR4 strip as the main purpose of our
discussion here.

Nevertheless, the pc run data is very valuable for our discussion.

I know you are very careful to present data to show the feasibility, but not
to be misinterpreted as problem free.  I like to add a few observation to
emphasize that 20" FR4 strip is not problem free at the data rate of 3.12

1. Even with the "Emphasis High", the RJ (135 ps)is too high, which is 43%
of a bit cell time (312 ps) caused by the strip.  The RJ can not be cleared
by deskew circuit, and will be added to the output of the deskew circuit.
We may have the excessive link jitter problem in a real system. The BER test
using an equipment does not include DJ+RJ by other components in a link.

Referencing data:	(15.01^2 - 11.76^2)^0.5 = 9.64 ps
			Therefore: RJ = 14x9.64 = 135 ps

2. The Pre-emphasis, and Post-emphasis are effective, if the length is
pre-defined.  In real applications, the strip lengths are all different to
cause the emphasis technique not only infective, but it may make it worse.
Unless, we can pre-determine the strip length regardless of any
pplication  -- it is impossible to do so.

3. Another concern is the PCB space availability.
	The GbE serdes of 64-pin FQFO package has pin-to-pin pitch of 20 mil (0.5
mm).  However, the micro strip of a differential pair needs 50 mil spacing
(35 mil + 15 mil) is far too large  to fit into the 20 mil space available.
Unless, the 8 differential pairs are spread out around a SERDES chip --
mixing of high frequency and logic signals is questionable practice.

These are just a few issues to show that there are a huge gap between
Feasibility test and Qualification test.  There are many other issues which
are not mentioned yet.  We still need a lot of work to make it a viable
product.  For example, cut the maxim length back from 20" to less than 10",
and limit the number of edge connector connections to two max.  If we can
not use edge connector in a back plane, our production cost will go up

Again, I agree that 3.125 Gbps in LSI CMOS technology is Feasible.


Ed Chang
NetWorth technologies, Inc.

-----Original Message-----
From: owner-stds-802-3-hssg@xxxxxxxx
[mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Mike Jenkins
Sent: Wednesday, November 24, 1999 5:20 PM
To: stds-802-3-hssg@xxxxxxxx
Subject: Re: HARI Systems Design

Larry, et al,

The presentation below, given at the November HSSG, shows 3.125Gbaud
signals thru 20 inches of FR-4 PCB plus two (SMA) connectors plus 1M
of cable plus a BGA socket.  The eye opening shown should not pose
a challenge to any reasonable serdes.  The circuit technique LSI uses
to open the eye is pre-emphasis.  Other vendors use post-emphasis,
but same result, I'm sure.

Admittedly, this is nominal hardware, but no exotic materials.
I believe that not much frequency content above 1.5G is needed for a
good signal at 3G (as the waveforms in the presentation suggest).
As the HARI electrical spec evolved, admittedly, I, too, was concerned
about the relative loosening of the impedance tolerance.  I tried
to show a problem with simulations, but could not.  The most relevant
electrical spec to limit reflections is the return loss, which
effectively constrains capacitive and inductive parasitics as well
as line mismatch.  I think the HARI electrical spec has it about
right (and I am a veteran of MANY applications of our gigabit and
two gigabit serdes).

All the above is not meant to say there are no problems in HARI.
As one of the loyal opposition within HARI, here is my standard rant:
The coding scheme as presently defined is "byte striped".  That is,
serdes can discern no larger group than 10 bits.  The data path per
HARI lane is then 1-byte wide, running at 312 MHz.  Deskew will
require parallel operations across all four (skewed) lanes at this
speed.  This is going to cause considerable implementation pain.
Both Gigabit Ethernet and Fibre Channel architectures to date
permitted at least 2-byte wide data paths.  This scheme will not.
To coopt Joel's aphorism, the ASIC designer will have to "come up
with last minute desperate solutions to impossible problems caused
by the System Architect."

For an alternative coding proposal ("word striped") founded on
considerable experience, please see:

Mike Jenkins

Larry Miller wrote:
> How long of traces are you getting on FR-4? Have you actually fabricated
> these?
> Our network analyzer tests indicate that FR-4 dies horribly (lossy) above
> about 1.5 Gb/s. By the time we get to 3 GHz all the analyzer is displaying
> is the analyzer receiver input noise, looking in vain for signals......
> (HP8752C)
> Your Tricks & Tips look like they would help, but I would be very
> interested in hearing from anyone who claims to have successfully used
> in 5+ GHz circuits over more than 3-4 inches and, if so, what kind of
> Thanks,
> Larry Miller
 Mike Jenkins               Phone: 408.433.7901            _____
 LSI Logic Corp, ms/G715      Fax: 408.433.7461        LSI|LOGIC| (R)
 1525 McCarthy Blvd.       mailto:Jenkins@xxxxxxxx        |     |
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